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CPU refactoring - move SIMD (scalar and vector) instructions to separate files by category, remove AILConv and use only the methods inside SIMD helper to extract/insert vector elements

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This commit is contained in:
gdkchan 2018-02-17 18:06:11 -03:00
parent 10bf1735a6
commit 028a9f99ab
24 changed files with 2551 additions and 2610 deletions
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108
Ryujinx/Cpu/Translation/AILEmitterCtx.cs
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@ -150,8 +150,8 @@ namespace ChocolArm64.Translation
if (LastCmpOp != null && LastFlagOp == LastCmpOp && BranchOps.ContainsKey(Cond))
{
Ldloc(Tmp3Index, AIoType.Int, GetIntType(LastCmpOp));
Ldloc(Tmp4Index, AIoType.Int, GetIntType(LastCmpOp));
Ldloc(Tmp3Index, AIoType.Int, LastCmpOp.RegisterSize);
Ldloc(Tmp4Index, AIoType.Int, LastCmpOp.RegisterSize);
if (LastCmpOp.Emitter == AInstEmit.Adds)
{
@ -353,12 +353,6 @@ namespace ChocolArm64.Translation
public void EmitLdvec(int Index) => Ldloc(Index, AIoType.Vector);
public void EmitStvec(int Index) => Stloc(Index, AIoType.Vector);
public void EmitLdvecsi(int Index) => Ldloc(Index, AIoType.VectorI);
public void EmitStvecsi(int Index) => Stloc(Index, AIoType.VectorI);
public void EmitLdvecsf(int Index) => Ldloc(Index, AIoType.VectorF);
public void EmitStvecsf(int Index) => Stloc(Index, AIoType.VectorF);
public void EmitLdflg(int Index) => Ldloc(Index, AIoType.Flag);
public void EmitStflg(int Index)
{
@ -369,107 +363,17 @@ namespace ChocolArm64.Translation
private void Ldloc(int Index, AIoType IoType)
{
ILBlock.Add(new AILOpCodeLoad(Index, IoType, GetOperType(IoType)));
ILBlock.Add(new AILOpCodeLoad(Index, IoType, CurrOp.RegisterSize));
}
private void Ldloc(int Index, AIoType IoType, Type Type)
private void Ldloc(int Index, AIoType IoType, ARegisterSize RegisterSize)
{
ILBlock.Add(new AILOpCodeLoad(Index, IoType, Type));
ILBlock.Add(new AILOpCodeLoad(Index, IoType, RegisterSize));
}
private void Stloc(int Index, AIoType IoType)
{
ILBlock.Add(new AILOpCodeStore(Index, IoType, GetOutOperType(IoType)));
}
private Type GetOutOperType(AIoType IoType)
{
//This instruction is used to convert between floating point
//types, so the input and output types are different.
if (CurrOp.Emitter == AInstEmit.Fcvt_S)
{
return GetFloatType(((AOpCodeSimd)CurrOp).Opc);
}
else
{
return GetOperType(IoType);
}
}
private Type GetOperType(AIoType IoType)
{
switch (IoType & AIoType.Mask)
{
case AIoType.Flag: return typeof(bool);
case AIoType.Int: return GetIntType(CurrOp);
case AIoType.Vector: return GetVecType(CurrOp, IoType);
}
throw new ArgumentException(nameof(IoType));
}
private Type GetIntType(AOpCode OpCode)
{
//Always default to 64-bits.
return OpCode.RegisterSize == ARegisterSize.Int32
? typeof(uint)
: typeof(ulong);
}
private Type GetVecType(AOpCode OpCode, AIoType IoType)
{
if (!(OpCode is IAOpCodeSimd Op))
{
return typeof(AVec);
}
int Size = Op.Size;
if (Op.Emitter == AInstEmit.Fmov_Ftoi ||
Op.Emitter == AInstEmit.Fmov_Itof)
{
Size |= 2;
}
if ((Op is AOpCodeMem || Op is IAOpCodeLit) &&
!(Op is AOpCodeSimdMemMs || Op is AOpCodeSimdMemSs))
{
return Size < 4 ? typeof(ulong) : typeof(AVec);
}
else if (IoType == AIoType.VectorI)
{
return GetIntType(Size);
}
else if (IoType == AIoType.VectorF)
{
return GetFloatType(Size);
}
return typeof(AVec);
}
private static Type GetIntType(int Size)
{
switch (Size)
{
case 0: return typeof(byte);
case 1: return typeof(ushort);
case 2: return typeof(uint);
case 3: return typeof(ulong);
}
throw new ArgumentOutOfRangeException(nameof(Size));
}
private static Type GetFloatType(int Size)
{
switch (Size)
{
case 0: return typeof(float);
case 1: return typeof(double);
}
throw new ArgumentOutOfRangeException(nameof(Size));
ILBlock.Add(new AILOpCodeStore(Index, IoType, CurrOp.RegisterSize));
}
public void EmitCallPropGet(Type ObjType, string PropName)