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Implement a new JIT for Arm devices (#6057)
* Implement a new JIT for Arm devices * Auto-format * Make a lot of Assembler members read-only * More read-only * Fix more warnings * ObjectDisposedException.ThrowIf * New JIT cache for platforms that enforce W^X, currently unused * Remove unused using * Fix assert * Pass memory manager type around * Safe memory manager mode support + other improvements * Actual safe memory manager mode masking support * PR feedback
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gdkchan
GitHub
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331c07807f
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427b7d06b5
135 changed files with 43322 additions and 24 deletions
265
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitGE.cs
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265
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitGE.cs
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using Ryujinx.Cpu.LightningJit.CodeGen;
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using Ryujinx.Cpu.LightningJit.CodeGen.Arm64;
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namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
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{
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static class InstEmitGE
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{
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public static void Sadd16(CodeGenContext context, uint rd, uint rn, uint rm)
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{
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EmitAddSub(context, rd, rn, rm, is16Bit: true, add: true, unsigned: false);
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}
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public static void Sadd8(CodeGenContext context, uint rd, uint rn, uint rm)
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{
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EmitAddSub(context, rd, rn, rm, is16Bit: false, add: true, unsigned: false);
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}
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public static void Sasx(CodeGenContext context, uint rd, uint rn, uint rm)
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{
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EmitAsxSax(context, rd, rn, rm, isAsx: true, unsigned: false);
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}
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public static void Sel(CodeGenContext context, uint rd, uint rn, uint rm)
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{
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Operand rdOperand = InstEmitCommon.GetOutputGpr(context, rd);
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Operand rnOperand = InstEmitCommon.GetInputGpr(context, rn);
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Operand rmOperand = InstEmitCommon.GetInputGpr(context, rm);
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using ScopedRegister geFlags = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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using ScopedRegister tempRegister = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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ExtractGEFlags(context, geFlags.Operand);
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// Broadcast compact GE flags (one bit to one byte, 0b1111 -> 0x1010101).
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context.Arm64Assembler.Mov(tempRegister.Operand, 0x204081u);
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context.Arm64Assembler.Mul(geFlags.Operand, geFlags.Operand, tempRegister.Operand);
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context.Arm64Assembler.And(geFlags.Operand, geFlags.Operand, InstEmitCommon.Const(0x1010101));
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// Build mask from expanded flags (0x1010101 -> 0xFFFFFFFF).
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context.Arm64Assembler.Lsl(tempRegister.Operand, geFlags.Operand, InstEmitCommon.Const(8));
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context.Arm64Assembler.Sub(geFlags.Operand, tempRegister.Operand, geFlags.Operand);
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// Result = (n & mask) | (m & ~mask).
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context.Arm64Assembler.And(tempRegister.Operand, geFlags.Operand, rnOperand);
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context.Arm64Assembler.Bic(rdOperand, rmOperand, geFlags.Operand);
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context.Arm64Assembler.Orr(rdOperand, rdOperand, tempRegister.Operand);
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}
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public static void Ssax(CodeGenContext context, uint rd, uint rn, uint rm)
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{
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EmitAsxSax(context, rd, rn, rm, isAsx: false, unsigned: false);
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}
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public static void Ssub16(CodeGenContext context, uint rd, uint rn, uint rm)
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{
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EmitAddSub(context, rd, rn, rm, is16Bit: true, add: false, unsigned: false);
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}
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public static void Ssub8(CodeGenContext context, uint rd, uint rn, uint rm)
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{
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EmitAddSub(context, rd, rn, rm, is16Bit: false, add: false, unsigned: false);
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}
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public static void Uadd16(CodeGenContext context, uint rd, uint rn, uint rm)
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{
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EmitAddSub(context, rd, rn, rm, is16Bit: true, add: true, unsigned: true);
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}
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public static void Uadd8(CodeGenContext context, uint rd, uint rn, uint rm)
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{
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EmitAddSub(context, rd, rn, rm, is16Bit: false, add: true, unsigned: true);
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}
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public static void Uasx(CodeGenContext context, uint rd, uint rn, uint rm)
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{
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EmitAsxSax(context, rd, rn, rm, isAsx: true, unsigned: true);
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}
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public static void Usax(CodeGenContext context, uint rd, uint rn, uint rm)
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{
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EmitAsxSax(context, rd, rn, rm, isAsx: false, unsigned: true);
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}
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public static void Usub16(CodeGenContext context, uint rd, uint rn, uint rm)
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{
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EmitAddSub(context, rd, rn, rm, is16Bit: true, add: false, unsigned: true);
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}
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public static void Usub8(CodeGenContext context, uint rd, uint rn, uint rm)
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{
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EmitAddSub(context, rd, rn, rm, is16Bit: false, add: false, unsigned: true);
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}
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private static void EmitAddSub(CodeGenContext context, uint rd, uint rn, uint rm, bool is16Bit, bool add, bool unsigned)
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{
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Operand rdOperand = InstEmitCommon.GetOutputGpr(context, rd);
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Operand rnOperand = InstEmitCommon.GetInputGpr(context, rn);
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Operand rmOperand = InstEmitCommon.GetInputGpr(context, rm);
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using ScopedRegister geFlags = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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int e = 0;
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void Emit(Operand d, Operand n, Operand m)
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{
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if (add)
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{
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context.Arm64Assembler.Add(d, n, m);
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}
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else
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{
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context.Arm64Assembler.Sub(d, n, m);
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}
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if (unsigned && add)
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{
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if (e == 0)
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{
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context.Arm64Assembler.Lsr(geFlags.Operand, d, InstEmitCommon.Const(is16Bit ? 16 : 8));
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}
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else
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{
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using ScopedRegister tempRegister = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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context.Arm64Assembler.Lsr(tempRegister.Operand, d, InstEmitCommon.Const(is16Bit ? 16 : 8));
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context.Arm64Assembler.Orr(geFlags.Operand, geFlags.Operand, tempRegister.Operand, ArmShiftType.Lsl, e);
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}
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}
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else
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{
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using ScopedRegister tempRegister = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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context.Arm64Assembler.Mvn(tempRegister.Operand, d);
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if (e == 0)
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{
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context.Arm64Assembler.Lsr(geFlags.Operand, tempRegister.Operand, InstEmitCommon.Const(31));
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}
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else
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{
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context.Arm64Assembler.Lsr(tempRegister.Operand, tempRegister.Operand, InstEmitCommon.Const(31));
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context.Arm64Assembler.Orr(geFlags.Operand, geFlags.Operand, tempRegister.Operand, ArmShiftType.Lsl, e);
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}
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}
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e += is16Bit ? 2 : 1;
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}
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if (is16Bit)
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{
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if (unsigned)
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{
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InstEmitCommon.EmitUnsigned16BitPair(context, rd, rn, rm, Emit);
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}
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else
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{
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InstEmitCommon.EmitSigned16BitPair(context, rd, rn, rm, Emit);
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}
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// Duplicate bits.
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context.Arm64Assembler.Orr(geFlags.Operand, geFlags.Operand, geFlags.Operand, ArmShiftType.Lsl, 1);
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}
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else
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{
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if (unsigned)
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{
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InstEmitCommon.EmitUnsigned8BitPair(context, rd, rn, rm, Emit);
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}
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else
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{
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InstEmitCommon.EmitSigned8BitPair(context, rd, rn, rm, Emit);
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}
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}
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UpdateGEFlags(context, geFlags.Operand);
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}
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private static void EmitAsxSax(CodeGenContext context, uint rd, uint rn, uint rm, bool isAsx, bool unsigned)
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{
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Operand rdOperand = InstEmitCommon.GetOutputGpr(context, rd);
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Operand rnOperand = InstEmitCommon.GetInputGpr(context, rn);
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Operand rmOperand = InstEmitCommon.GetInputGpr(context, rm);
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using ScopedRegister geFlags = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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void Emit(Operand d, Operand n, Operand m, int e)
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{
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bool add = e == (isAsx ? 1 : 0);
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if (add)
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{
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context.Arm64Assembler.Add(d, n, m);
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}
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else
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{
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context.Arm64Assembler.Sub(d, n, m);
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}
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if (unsigned && add)
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{
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if (e == 0)
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{
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context.Arm64Assembler.Lsr(geFlags.Operand, d, InstEmitCommon.Const(16));
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}
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else
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{
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using ScopedRegister tempRegister = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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context.Arm64Assembler.Lsr(tempRegister.Operand, d, InstEmitCommon.Const(16));
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context.Arm64Assembler.Orr(geFlags.Operand, geFlags.Operand, tempRegister.Operand, ArmShiftType.Lsl, e * 2);
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}
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}
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else
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{
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using ScopedRegister tempRegister = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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context.Arm64Assembler.Mvn(tempRegister.Operand, d);
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if (e == 0)
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{
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context.Arm64Assembler.Lsr(geFlags.Operand, tempRegister.Operand, InstEmitCommon.Const(31));
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}
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else
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{
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context.Arm64Assembler.Lsr(tempRegister.Operand, tempRegister.Operand, InstEmitCommon.Const(31));
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context.Arm64Assembler.Orr(geFlags.Operand, geFlags.Operand, tempRegister.Operand, ArmShiftType.Lsl, e * 2);
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}
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}
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}
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if (unsigned)
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{
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InstEmitCommon.EmitUnsigned16BitXPair(context, rd, rn, rm, Emit);
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}
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else
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{
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InstEmitCommon.EmitSigned16BitXPair(context, rd, rn, rm, Emit);
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}
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// Duplicate bits.
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context.Arm64Assembler.Orr(geFlags.Operand, geFlags.Operand, geFlags.Operand, ArmShiftType.Lsl, 1);
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UpdateGEFlags(context, geFlags.Operand);
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}
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public static void UpdateGEFlags(CodeGenContext context, Operand flags)
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{
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Operand ctx = InstEmitSystem.Register(context.RegisterAllocator.FixedContextRegister);
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using ScopedRegister tempRegister = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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context.Arm64Assembler.LdrRiUn(tempRegister.Operand, ctx, NativeContextOffsets.FlagsBaseOffset);
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context.Arm64Assembler.Bfi(tempRegister.Operand, flags, 16, 4);
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context.Arm64Assembler.StrRiUn(tempRegister.Operand, ctx, NativeContextOffsets.FlagsBaseOffset);
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}
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public static void ExtractGEFlags(CodeGenContext context, Operand flags)
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{
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Operand ctx = InstEmitSystem.Register(context.RegisterAllocator.FixedContextRegister);
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context.Arm64Assembler.LdrRiUn(flags, ctx, NativeContextOffsets.FlagsBaseOffset);
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context.Arm64Assembler.Ubfx(flags, flags, 16, 4);
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}
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}
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}
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