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Add FCVTAS and FCVTAU instructions

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This commit is contained in:
gdkchan 2018-02-17 18:59:37 -03:00
parent ebddc40550
commit 595e7ee588
4 changed files with 68 additions and 24 deletions
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35
Ryujinx/Cpu/Instruction/AInstEmitSimdCvt.cs
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@ -21,6 +21,16 @@ namespace ChocolArm64.Instruction
EmitScalarSetF(Context, Op.Rd, Op.Opc);
}
public static void Fcvtas_Gp(AILEmitterCtx Context)
{
Fcvta__Gp(Context, Signed: true);
}
public static void Fcvtau_Gp(AILEmitterCtx Context)
{
Fcvta__Gp(Context, Signed: false);
}
public static void Fcvtms_Gp(AILEmitterCtx Context)
{
EmitFcvt_s_Gp(Context, nameof(Math.Floor));
@ -155,6 +165,31 @@ namespace ChocolArm64.Instruction
}
}
private static void Fcvta__Gp(AILEmitterCtx Context, bool Signed)
{
AOpCodeSimdCvt Op = (AOpCodeSimdCvt)Context.CurrOp;
EmitVectorExtractF(Context, Op.Rn, 0, Op.Size);
EmitRoundMathCall(Context, MidpointRounding.AwayFromZero);
if (Signed)
{
EmitScalarFcvts(Context, Op.Size, 0);
}
else
{
EmitScalarFcvtu(Context, Op.Size, 0);
}
if (Context.CurrOp.RegisterSize == ARegisterSize.Int32)
{
Context.Emit(OpCodes.Conv_U8);
}
Context.EmitStintzr(Op.Rd);
}
private static void EmitFcvt_s_Gp(AILEmitterCtx Context, string Name)
{
AOpCodeSimdCvt Op = (AOpCodeSimdCvt)Context.CurrOp;