crafterpika/MeloNX
0
0
Fork 0
mirror of https://git.743378673.xyz/MeloNX/MeloNX.git synced 2025-08-02 18:17:10 +02:00
Code Issues Projects Releases Packages Wiki Activity

Rename ARegisters to AThreadState

Browse source
This commit is contained in:
gdkchan 2018-02-18 16:28:07 -03:00
parent 5a0396efaf
commit f35d286c8d
25 changed files with 303 additions and 301 deletions
Download patch file Download diff file Expand all files Collapse all files

5
Ryujinx/Cpu/Instruction/AInstEmitAlu.cs
View file

@ -343,8 +343,11 @@ namespace ChocolArm64.Instruction
private static void EmitZeroCVFlags(AILEmitterCtx Context)
{
Context.EmitLdc_I4(0);
Context.EmitLdc_I4(0);
Context.EmitStflg((int)APState.VBit);
Context.EmitLdc_I4(0);
Context.EmitStflg((int)APState.CBit);
}
}

14
Ryujinx/Cpu/Instruction/AInstEmitException.cs
View file

@ -11,12 +11,12 @@ namespace ChocolArm64.Instruction
public static void Brk(AILEmitterCtx Context)
{
EmitExceptionCall(Context, nameof(ARegisters.OnBreak));
EmitExceptionCall(Context, nameof(AThreadState.OnBreak));
}
public static void Svc(AILEmitterCtx Context)
{
EmitExceptionCall(Context, nameof(ARegisters.OnSvcCall));
EmitExceptionCall(Context, nameof(AThreadState.OnSvcCall));
}
private static void EmitExceptionCall(AILEmitterCtx Context, string MthdName)
@ -25,11 +25,11 @@ namespace ChocolArm64.Instruction
Context.EmitStoreState();
Context.EmitLdarg(ATranslatedSub.RegistersArgIdx);
Context.EmitLdarg(ATranslatedSub.StateArgIdx);
Context.EmitLdc_I4(Op.Id);
MethodInfo MthdInfo = typeof(ARegisters).GetMethod(MthdName, Binding);
MethodInfo MthdInfo = typeof(AThreadState).GetMethod(MthdName, Binding);
Context.EmitCall(MthdInfo);
@ -45,14 +45,14 @@ namespace ChocolArm64.Instruction
Context.EmitStoreState();
Context.EmitLdarg(ATranslatedSub.RegistersArgIdx);
Context.EmitLdarg(ATranslatedSub.StateArgIdx);
Context.EmitLdc_I8(Op.Position);
Context.EmitLdc_I4(Op.RawOpCode);
string MthdName = nameof(ARegisters.OnUndefined);
string MthdName = nameof(AThreadState.OnUndefined);
MethodInfo MthdInfo = typeof(ARegisters).GetMethod(MthdName, Binding);
MethodInfo MthdInfo = typeof(AThreadState).GetMethod(MthdName, Binding);
Context.EmitCall(MthdInfo);

6
Ryujinx/Cpu/Instruction/AInstEmitFlow.cs
View file

@ -26,7 +26,7 @@ namespace ChocolArm64.Instruction
AOpCodeBImmAl Op = (AOpCodeBImmAl)Context.CurrOp;
Context.EmitLdc_I(Op.Position + 4);
Context.EmitStint(ARegisters.LRIndex);
Context.EmitStint(AThreadState.LRIndex);
Context.EmitStoreState();
if (Context.TryOptEmitSubroutineCall())
@ -66,7 +66,7 @@ namespace ChocolArm64.Instruction
AOpCodeBReg Op = (AOpCodeBReg)Context.CurrOp;
Context.EmitLdc_I(Op.Position + 4);
Context.EmitStint(ARegisters.LRIndex);
Context.EmitStint(AThreadState.LRIndex);
Context.EmitStoreState();
Context.EmitLdintzr(Op.Rn);
@ -99,7 +99,7 @@ namespace ChocolArm64.Instruction
public static void Ret(AILEmitterCtx Context)
{
Context.EmitStoreState();
Context.EmitLdint(ARegisters.LRIndex);
Context.EmitLdint(AThreadState.LRIndex);
Context.Emit(OpCodes.Ret);
}

2
Ryujinx/Cpu/Instruction/AInstEmitMemoryEx.cs
View file

@ -159,7 +159,7 @@ namespace ChocolArm64.Instruction
private static void EmitMemoryCall(AILEmitterCtx Context, string Name, int Rn = -1)
{
Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
Context.EmitLdarg(ATranslatedSub.RegistersArgIdx);
Context.EmitLdarg(ATranslatedSub.StateArgIdx);
if (Rn != -1)
{

2
Ryujinx/Cpu/Instruction/AInstEmitSimdMemory.cs
View file

@ -167,7 +167,7 @@ namespace ChocolArm64.Instruction
Context.EmitLdint(Op.Rn);
if (Op.Rm != ARegisters.ZRIndex)
if (Op.Rm != AThreadState.ZRIndex)
{
Context.EmitLdint(Op.Rm);
}

34
Ryujinx/Cpu/Instruction/AInstEmitSystem.cs
View file

@ -13,26 +13,26 @@ namespace ChocolArm64.Instruction
{
AOpCodeSystem Op = (AOpCodeSystem)Context.CurrOp;
Context.EmitLdarg(ATranslatedSub.RegistersArgIdx);
Context.EmitLdarg(ATranslatedSub.StateArgIdx);
string PropName;
switch (GetPackedId(Op))
{
case 0b11_011_0000_0000_001: PropName = nameof(ARegisters.CtrEl0); break;
case 0b11_011_0000_0000_111: PropName = nameof(ARegisters.DczidEl0); break;
case 0b11_011_0100_0100_000: PropName = nameof(ARegisters.Fpcr); break;
case 0b11_011_0100_0100_001: PropName = nameof(ARegisters.Fpsr); break;
case 0b11_011_1101_0000_010: PropName = nameof(ARegisters.TpidrEl0); break;
case 0b11_011_1101_0000_011: PropName = nameof(ARegisters.Tpidr); break;
case 0b11_011_1110_0000_001: PropName = nameof(ARegisters.CntpctEl0); break;
case 0b11_011_0000_0000_001: PropName = nameof(AThreadState.CtrEl0); break;
case 0b11_011_0000_0000_111: PropName = nameof(AThreadState.DczidEl0); break;
case 0b11_011_0100_0100_000: PropName = nameof(AThreadState.Fpcr); break;
case 0b11_011_0100_0100_001: PropName = nameof(AThreadState.Fpsr); break;
case 0b11_011_1101_0000_010: PropName = nameof(AThreadState.TpidrEl0); break;
case 0b11_011_1101_0000_011: PropName = nameof(AThreadState.Tpidr); break;
case 0b11_011_1110_0000_001: PropName = nameof(AThreadState.CntpctEl0); break;
default: throw new NotImplementedException($"Unknown MRS at {Op.Position:x16}");
}
Context.EmitCallPropGet(typeof(ARegisters), PropName);
Context.EmitCallPropGet(typeof(AThreadState), PropName);
PropertyInfo PropInfo = typeof(ARegisters).GetProperty(PropName);
PropertyInfo PropInfo = typeof(AThreadState).GetProperty(PropName);
if (PropInfo.PropertyType != typeof(long) &&
PropInfo.PropertyType != typeof(ulong))
@ -47,21 +47,21 @@ namespace ChocolArm64.Instruction
{
AOpCodeSystem Op = (AOpCodeSystem)Context.CurrOp;
Context.EmitLdarg(ATranslatedSub.RegistersArgIdx);
Context.EmitLdarg(ATranslatedSub.StateArgIdx);
Context.EmitLdintzr(Op.Rt);
string PropName;
switch (GetPackedId(Op))
{
case 0b11_011_0100_0100_000: PropName = nameof(ARegisters.Fpcr); break;
case 0b11_011_0100_0100_001: PropName = nameof(ARegisters.Fpsr); break;
case 0b11_011_1101_0000_010: PropName = nameof(ARegisters.TpidrEl0); break;
case 0b11_011_0100_0100_000: PropName = nameof(AThreadState.Fpcr); break;
case 0b11_011_0100_0100_001: PropName = nameof(AThreadState.Fpsr); break;
case 0b11_011_1101_0000_010: PropName = nameof(AThreadState.TpidrEl0); break;
default: throw new NotImplementedException($"Unknown MSR at {Op.Position:x16}");
}
PropertyInfo PropInfo = typeof(ARegisters).GetProperty(PropName);
PropertyInfo PropInfo = typeof(AThreadState).GetProperty(PropName);
if (PropInfo.PropertyType != typeof(long) &&
PropInfo.PropertyType != typeof(ulong))
@ -69,7 +69,7 @@ namespace ChocolArm64.Instruction
Context.Emit(OpCodes.Conv_U4);
}
Context.EmitCallPropSet(typeof(ARegisters), PropName);
Context.EmitCallPropSet(typeof(AThreadState), PropName);
}
public static void Nop(AILEmitterCtx Context)
@ -89,7 +89,7 @@ namespace ChocolArm64.Instruction
case 0b11_011_0111_0100_001:
{
//DC ZVA
for (int Offs = 0; Offs < (4 << ARegisters.DczSizeLog2); Offs += 8)
for (int Offs = 0; Offs < (4 << AThreadState.DczSizeLog2); Offs += 8)
{
Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
Context.EmitLdint(Op.Rt);