9 commits

Author	SHA1	Message	Date
gdkchan	028a9f99ab	CPU refactoring - move SIMD (scalar and vector) instructions to separate files by category, remove AILConv and use only the methods inside SIMD helper to extract/insert vector elements	2018-02-17 18:06:11 -03:00
gdkchan	8e0785ca24	Emit CIL directly for more SIMD instructions, add UCVTF (vector, scalar) and UZP2, fix XTN (?)	2018-02-15 01:32:25 -03:00
gdkchan	cf8cc418c3	Generate CIL for SCVTF (vector), add undefined encodings for some instructions	2018-02-12 00:37:20 -03:00
gdkchan	9746069232	Only throw undefined instruction exception at execution, not at translation stage	2018-02-10 14:20:46 -03:00
gdkchan	b52f96b81b	Add BRK instruction, fix wrong namespace on one of Am interfaces, and disable Debug/Trace logs by default	2018-02-10 10:24:16 -03:00
gdkchan	411949eeac	Move a few more SIMD instructions to emit CIL directly instead of a method call	2018-02-09 17:14:47 -03:00
gdkchan	c1198d7816	Add FVCTZS (fixed point variant) and LD1 (single structure variant) instructions	2018-02-09 00:26:20 -03:00
gdkchan	12688bd8b2	Add FMADD and FMSUB instructions	2018-02-07 20:07:16 -03:00
gdkchan	b7e1d9930d	aloha	2018-02-04 20:08:20 -03:00