4 commits

Author	SHA1	Message	Date
gdkchan	028a9f99ab	CPU refactoring - move SIMD (scalar and vector) instructions to separate files by category, remove AILConv and use only the methods inside SIMD helper to extract/insert vector elements	2018-02-17 18:06:11 -03:00
gdkchan	8e0785ca24	Emit CIL directly for more SIMD instructions, add UCVTF (vector, scalar) and UZP2, fix XTN (?)	2018-02-15 01:32:25 -03:00
gdkchan	9746069232	Only throw undefined instruction exception at execution, not at translation stage	2018-02-10 14:20:46 -03:00
gdkchan	c1198d7816	Add FVCTZS (fixed point variant) and LD1 (single structure variant) instructions	2018-02-09 00:26:20 -03:00

Renamed from Ryujinx/Cpu/Decoder/AOpCodeSimdMemMult.cs (Browse further)