8 commits

Author	SHA1	Message	Date
gdkchan	028a9f99ab	CPU refactoring - move SIMD (scalar and vector) instructions to separate files by category, remove AILConv and use only the methods inside SIMD helper to extract/insert vector elements	2018-02-17 18:06:11 -03:00
gdkchan	8e0785ca24	Emit CIL directly for more SIMD instructions, add UCVTF (vector, scalar) and UZP2, fix XTN (?)	2018-02-15 01:32:25 -03:00
gdkchan	2e71b0dcb2	Made initial implementation of the thread scheduler, refactor Svc to avoid passing many arguments	2018-02-13 23:43:08 -03:00
gdkchan	cf8cc418c3	Generate CIL for SCVTF (vector), add undefined encodings for some instructions	2018-02-12 00:37:20 -03:00
gdkchan	411949eeac	Move a few more SIMD instructions to emit CIL directly instead of a method call	2018-02-09 17:14:47 -03:00
gdkchan	c1198d7816	Add FVCTZS (fixed point variant) and LD1 (single structure variant) instructions	2018-02-09 00:26:20 -03:00
gdkchan	976155406e	Removed parts of the MMU functionality to use memory directly (faster, but potentially more dangerous, WIP), also changed the Shl/Sshr immediate instructions to use IL instead of calling the method	2018-02-07 13:44:48 -03:00
gdkchan	b7e1d9930d	aloha	2018-02-04 20:08:20 -03:00