gdkchan
107487c242
Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits ( #225 )
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* Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions
* Address PR feedback
* Address PR feedback
* Remove another useless temp var
* nit: Alignment
* Replace Context.CurrOp.GetBitsCount() with Op.GetBitsCount()
* Fix encodings and move flag bit test out of the loop
2018-07-14 13:13:02 -03:00
Merry
19538dd48c
ChocolArm64: More accurate implementation of Frecpe & Frecps ( #228 )
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* ChocolArm64: More accurate implementation of Frecpe
* ChocolArm64: Handle infinities and zeros in Frecps
2018-07-08 16:54:47 -03:00
gdkchan
2cab46ba5a
Add SMAXP, SMINP, UMAX, UMAXP, UMIN and UMINP cpu instructions ( #200 )
2018-07-03 03:31:48 -03:00
LDj3SNuD
f306b74ab1
Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Improve CountSetBits8() algorithm. ( #212 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdLogical.cs
* Update AVectorHelper.cs
* Update ASoftFallback.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Improve CountSetBits8() algorithm.
* Improve CountSetBits8() algorithm.
2018-07-03 03:31:16 -03:00
LDj3SNuD
ff34ceaa3e
Add Saba_V, Sabal_V, Sabd_V, Sabdl_V, Uaba_V, Uabal_V; Update Uabd_V, Uabdl_V. Add 16 tests. ( #204 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Update Instructions.cs
* Update CpuTest.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
2018-06-30 12:40:41 -03:00
gdkchan
a2ceebf62c
Add support for the FMLA (by element/scalar) instruction ( #187 )
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* Add support for the FMLA (by element/scalar) instruction
* Fix encoding
2018-06-28 20:51:38 -03:00
LDj3SNuD
f246334568
Add Sqxtun_S, Sqxtun_V with 3 tests. ( #188 )
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* Update AInstEmitSimdArithmetic.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
2018-06-25 23:36:20 -03:00
LDj3SNuD
712974f827
Add Sse Opt. for Cmeq_V_2D, Cmgt_V_2D (Reg). Add Sse Opt. for Crc32cb, Crc32ch, Crc32cw, Crc32cx. Add 10 simple tests for Fcmgt, Fcmge, Fcmeq, Fcmle, Fcmlt (S, V) (Reg, Zero). Add 2 Cnt_V tests. ( #183 )
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* Add files via upload
* Add files via upload
* Add files via upload
* CPE
* Add EmitSse42Crc32()
* Update CpuTestSimdCmp.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimd.cs
* Update Instructions.cs
2018-06-25 22:32:29 -03:00
Rygnus
9dfc5c90f2
Add opcodes SQXTUN_S and SQXTUN_V ( #184 )
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* Add SQXTUN_S and SQXTUN_V
Part 1/2 of commit
* Add SQXTUN_S and SQXTUN_V (2/2)
Part 2/2 of commit
2018-06-25 14:23:46 -03:00
gdkchan
8ac10d1d97
Add the FADDP (scalar) instruction
2018-06-18 00:41:28 -03:00
Lordmau5
ffba9b94cf
Implement Fabs_V ( #146 )
2018-06-12 09:29:16 -03:00
gdkchan
9d789f99f9
Add intrinsics support ( #121 )
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* Initial intrinsics support
* Update tests to work with the new Vector128 type and intrinsics
* Drop SSE4.1 requirement
* Fix copy-paste mistake
2018-05-11 20:10:27 -03:00
LDj3SNuD
222045bf49
Add Sqxtn_S, Sqxtn_V, Uqxtn_S, Uqxtn_V instructions and Tests (6). ( #110 )
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* Update ILGeneratorEx.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
* Update CpuTest.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdArithmetic.cs
2018-04-29 20:39:58 -03:00
LDj3SNuD
e20c415768
Add Cls_V, Clz_V, Orn_V instructions. Add 18 Tests: And_V, Bic_V, Bif_V, Bit_V, Bsl_V, Cls_V, Clz_V, Orn_V, Orr_V. ( #104 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdLogical.cs
* Update AInstEmitSimdArithmetic.cs
* Update ASoftFallback.cs
* Update AInstEmitAlu.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update CpuTestSimdReg.cs
* Update CpuTestSimd.cs
2018-04-25 23:20:22 -03:00
LDj3SNuD
8d1872cc96
Add ADDHN{2}, RADDHN{2}, SUBHN{2}, RSUBHN{2} (vector) instructions. Add 8 Tests. ( #92 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update Pseudocode.cs
* Update Instructions.cs
* Update Bits.cs
* Create CpuTestSimd.cs
* Create CpuTestSimdReg.cs
* Update CpuTestSimd.cs
Provide a better supply of input values for the 20 Simd Tests.
* Update CpuTestSimdReg.cs
Provide a better supply of input values for the 20 Simd Tests.
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
2018-04-20 12:40:15 -03:00
MS-DOS1999
4c0da26c30
Fix Fmin/max and add vector version, add and modifying fmin/max tests ( #89 )
2018-04-19 00:22:12 -03:00
LDj3SNuD
7a306d9caa
Add ABS (scalar & vector), ADD (scalar), NEG (scalar) instructions. ( #88 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AOpCodeTable.cs
2018-04-18 10:56:27 -03:00
LDj3SNuD
bad6d9b7a0
Add FMUL (scalar, by element) instruction; add FRECPE, FRECPS (scalar & vector) instructions. Add 5 simple tests. ( #74 )
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* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Update CpuTestSimdArithmetic.cs
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
2018-04-08 16:08:57 -03:00
gdkchan
91d43b31f0
Fix FRSQRTS and FCM* (scalar) instructions
2018-04-06 10:20:17 -03:00
gdkchan
fe1d7c3c4d
Add FMLS (vector) instruction
2018-04-06 01:41:54 -03:00
gdkchan
02f34e39e1
Add FRSQRTS and FCM* instructions
2018-04-05 23:28:12 -03:00
Merry
0c986ce8c5
Implement Frsqrte_S ( #72 )
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* Implement Frsqrte_S
* Implement Frsqrte_V
* Add Frsqrte_S test
2018-04-05 20:36:19 -03:00
gdkchan
7d9a869b2e
Add Faddp (vector) instruction
2018-04-04 22:13:10 -03:00
gdkchan
ac6e677798
Add FNEG (vector) instruction
2018-04-04 16:36:07 -03:00
gdkchan
63c0199701
Fix EXT/Widening instruction carrying garbage values on some cases, fix ABD (it shouldn't accumulate, this is another variation of the instruction)
2018-03-30 17:37:31 -03:00
gdkchan
d884023579
Add UABD instruction
2018-03-30 16:30:23 -03:00
gdkchan
3594ead0ab
Add UABDL instruction
2018-03-30 16:16:16 -03:00
gdkchan
dc6b3fce12
Add UADDL instruction
2018-03-30 15:55:28 -03:00
gdkchan
d60d206cde
Add UHADD instruction
2018-03-30 12:37:07 -03:00
gdkchan
6268c2e3b4
Add FNMADD instruction
2018-03-24 00:28:23 -03:00
MS-DOS1999
3a7f42cc8e
Add Frint Instructions and Tests ( #62 )
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* add 'ADC 32bit and Overflow' test
* Add WZR/WSP tests
* fix ADC and ADDS
* add ADCS test
* add SBCS test
* indent my code and delete comment
* '/' <- i hate you x)
* remove spacebar char
* remove false tab
* add frintx_S test
* update frintx_S test
* add ASRV test
* fix new line
* fix PR
* fix indent
* Add add_V tests
* work on Frintx_V
* Add Frintx_V Instruction
* add some instruction and test
* Syntax + indent
* Delete Console Write
* Delete Console Write 2
* CR del
* Skip NaNs tests
* Skip NaNs tests 2
* Fix errors 1
* Fix errors 2
2018-03-23 07:40:23 -03:00
gdkchan
3a964ca287
Add MLA (vector by element), fixes some cases of MUL (vector by element)?
2018-03-15 22:36:47 -03:00
gdkchan
aefc052a40
Add FRINTM (vector) instruction
2018-03-09 23:41:05 -03:00
gdkchan
e6c0965ec7
Add SMLAL (vector), fix EXT instruction
2018-03-06 21:36:49 -03:00
gdkchan
bb27ad0a85
Add MUL (vector by element), fix FCVTN, make svcs use MakeError too
2018-03-05 16:18:37 -03:00
gdkchan
4b19910748
Add EXT, CMTST (vector) and UMULL (vector) instructions
2018-03-02 19:23:38 -03:00
gdkchan
4c3b282606
Add FABD (scalar), ADCS, SBCS instructions, update config with better default control mappings, update readme with the new mappings
2018-02-24 18:47:08 -03:00
gdkchan
6d640d712e
Fix cpu issue with cmp optimization, add HINT and FRINTX (scalar) instructions, fix for NvFlinger sometimes missing free buffers
2018-02-24 11:19:28 -03:00
gdkchan
16fe360767
Add FRINTP instruction, fix opcode ctor call method creation with multithreading
2018-02-22 16:26:11 -03:00
emmauss
bf5ccf25b7
Split main project into core,graphics and chocolarm4 subproject ( #29 )
2018-02-20 17:09:23 -03:00
