5 commits

Author	SHA1	Message	Date
LDj3SNuD	8fddc8351f	Add TRN1 & TRN2 (vector) instructions. Add 4 simple tests (4S, 8B). (#77) ... * Update AOpCodeTable.cs * Update AInstEmitSimdMove.cs * Update CpuTestSimdMove.cs * Update AInstEmitSimdMove.cs * Update CpuTestSimdMove.cs	2018-04-12 11:52:00 -03:00
gdkchan	63c0199701	Fix EXT/Widening instruction carrying garbage values on some cases, fix ABD (it shouldn't accumulate, this is another variation of the instruction)	2018-03-30 17:37:31 -03:00
gdkchan	e6c0965ec7	Add SMLAL (vector), fix EXT instruction	2018-03-06 21:36:49 -03:00
gdkchan	4b19910748	Add EXT, CMTST (vector) and UMULL (vector) instructions	2018-03-02 19:23:38 -03:00
emmauss	bf5ccf25b7	Split main project into core,graphics and chocolarm4 subproject (#29)	2018-02-20 17:09:23 -03:00

Renamed from Ryujinx/Cpu/Instruction/AInstEmitSimdMove.cs (Browse further)