6 commits

Author	SHA1	Message	Date
gdkchan	e8152c06e5	Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics (#405) ... * Optimize BIC, BSL, BIT, BIF, XTN, ZIP, DUP (Gp), FMADD (Scalar) and FCVT (Scalar) using SSE intrinsics, some CQ improvements * Remove useless space * Address PR feedback * Revert EmitVectorZero32_128 changes	2018-09-26 23:30:21 -03:00
gdkchan	0ea9a116ff	Zero out bits 63:32 of scalar float operations with SSE intrinsics (#273)	2018-08-14 23:54:12 -03:00
gdkchan	93a24a0ff2	More accurate impl of FMINNM/FMAXNM, add vector variants (#296) ... * More accurate impl of FMINNM/FMAXNM, add vector variants * Optimize for the 0 case when op1 != op2 * Address PR feedback	2018-08-05 02:54:21 -03:00
LDj3SNuD	f306b74ab1	Add Rbit_V instruction. Add 8 tests (Rbit_V; Rev16_V, Rev32_V, Rev64_V). Improve CountSetBits8() algorithm. (#212) ... * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdLogical.cs * Update AVectorHelper.cs * Update ASoftFallback.cs * Update Instructions.cs * Update CpuTestSimd.cs * Update CpuTestSimdReg.cs * Improve CountSetBits8() algorithm. * Improve CountSetBits8() algorithm.	2018-07-03 03:31:16 -03:00
gdkchan	d23b38662d	Add Sse2 fallback to Vector{Extract|Insert}Single methods on the CPU (#193)	2018-06-28 20:52:32 -03:00
gdkchan	9d789f99f9	Add intrinsics support (#121) ... * Initial intrinsics support * Update tests to work with the new Vector128 type and intrinsics * Drop SSE4.1 requirement * Fix copy-paste mistake	2018-05-11 20:10:27 -03:00