6 commits

Author	SHA1	Message	Date
gdkchan	107487c242	Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions, nits (#225) ... * Add SMLSL, SQRSHRN and SRSHR (Vector) cpu instructions * Address PR feedback * Address PR feedback * Remove another useless temp var * nit: Alignment * Replace Context.CurrOp.GetBitsCount() with Op.GetBitsCount() * Fix encodings and move flag bit test out of the loop	2018-07-14 13:13:02 -03:00
gdkchan	cb3fea6aaa	CPU fix for the cases using a Mask with shift = 0	2018-03-14 01:59:22 -03:00
gdkchan	5bdaf351a0	Add CRC32 instruction and SLI (vector)	2018-03-14 00:12:05 -03:00
gdkchan	475c64ede7	Fix EmitScalarUnaryOpF and add SSRA (vector)	2018-03-10 00:00:31 -03:00
gdkchan	4811d1acb1	Add SHLL instruction	2018-03-09 23:28:38 -03:00
emmauss	bf5ccf25b7	Split main project into core,graphics and chocolarm4 subproject (#29)	2018-02-20 17:09:23 -03:00

Renamed from Ryujinx/Cpu/Instruction/AInstEmitSimdShift.cs (Browse further)