From 00b784e046dfcbad239163bcd2213b74e6721e48 Mon Sep 17 00:00:00 2001 From: GreemDev Date: Wed, 2 Jul 2025 02:22:43 -0500 Subject: [PATCH] language feature: Extension Members: OperandType --- src/ARMeilleure/CodeGen/Arm64/Assembler.cs | 10 +- .../CodeGen/Arm64/CodeGenerator.cs | 78 +++++++-------- .../CodeGen/Arm64/CodeGeneratorIntrinsic.cs | 4 +- src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs | 26 ++--- .../CodeGen/Optimizations/Simplification.cs | 4 +- .../RegisterAllocators/CopyResolver.cs | 2 +- .../RegisterAllocators/HybridAllocator.cs | 18 ++-- .../RegisterAllocators/LinearScanAllocator.cs | 4 +- .../RegisterAllocators/StackAllocator.cs | 2 +- src/ARMeilleure/CodeGen/X86/Assembler.cs | 6 +- src/ARMeilleure/CodeGen/X86/CodeGenerator.cs | 94 +++++++++---------- src/ARMeilleure/CodeGen/X86/PreAllocator.cs | 16 ++-- .../CodeGen/X86/PreAllocatorSystemV.cs | 20 ++-- .../CodeGen/X86/PreAllocatorWindows.cs | 14 +-- .../Instructions/InstEmitHashHelper.cs | 2 +- .../IntermediateRepresentation/OperandType.cs | 32 +++---- 16 files changed, 161 insertions(+), 171 deletions(-) diff --git a/src/ARMeilleure/CodeGen/Arm64/Assembler.cs b/src/ARMeilleure/CodeGen/Arm64/Assembler.cs index 0d493426b..ee696c5f2 100644 --- a/src/ARMeilleure/CodeGen/Arm64/Assembler.cs +++ b/src/ARMeilleure/CodeGen/Arm64/Assembler.cs @@ -181,10 +181,10 @@ namespace ARMeilleure.CodeGen.Arm64 public void Fmov(Operand rd, Operand rn, bool topHalf) { - Debug.Assert(rd.Type.IsInteger() != rn.Type.IsInteger()); + Debug.Assert(rd.Type.IsInteger != rn.Type.IsInteger); Debug.Assert(rd.Type == OperandType.I64 || rn.Type == OperandType.I64 || !topHalf); - uint opcode = rd.Type.IsInteger() ? 0b110u : 0b111u; + uint opcode = rd.Type.IsInteger ? 0b110u : 0b111u; uint rmode = topHalf ? 1u << 19 : 0u; uint ftype = rd.Type == OperandType.FP64 || rn.Type == OperandType.FP64 ? 1u << 22 : 0u; @@ -411,7 +411,7 @@ namespace ARMeilleure.CodeGen.Arm64 public void Mov(Operand rd, Operand rn) { - if (rd.Type.IsInteger()) + if (rd.Type.IsInteger) { Orr(rd, Factory.Register(ZrRegister, RegisterType.Integer, rd.Type), rn); } @@ -973,7 +973,7 @@ namespace ARMeilleure.CodeGen.Arm64 uint instruction; int scale; - if (type.IsInteger()) + if (type.IsInteger) { instruction = intInst; @@ -1009,7 +1009,7 @@ namespace ARMeilleure.CodeGen.Arm64 { uint instruction; - if (type.IsInteger()) + if (type.IsInteger) { instruction = intInst; diff --git a/src/ARMeilleure/CodeGen/Arm64/CodeGenerator.cs b/src/ARMeilleure/CodeGen/Arm64/CodeGenerator.cs index a07d31284..320e86dc2 100644 --- a/src/ARMeilleure/CodeGen/Arm64/CodeGenerator.cs +++ b/src/ARMeilleure/CodeGen/Arm64/CodeGenerator.cs @@ -250,7 +250,7 @@ namespace ARMeilleure.CodeGen.Arm64 // ValidateBinOp(dest, src1, src2); - if (dest.Type.IsInteger()) + if (dest.Type.IsInteger) { context.Assembler.Add(dest, src1, src2); } @@ -268,7 +268,7 @@ namespace ARMeilleure.CodeGen.Arm64 ValidateBinOp(dest, src1, src2); - Debug.Assert(dest.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger); context.Assembler.And(dest, src1, src2); } @@ -281,7 +281,7 @@ namespace ARMeilleure.CodeGen.Arm64 ValidateBinOp(dest, src1, src2); - if (dest.Type.IsInteger()) + if (dest.Type.IsInteger) { context.Assembler.Eor(dest, src1, src2); } @@ -298,7 +298,7 @@ namespace ARMeilleure.CodeGen.Arm64 ValidateUnOp(dest, source); - Debug.Assert(dest.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger); context.Assembler.Mvn(dest, source); } @@ -311,7 +311,7 @@ namespace ARMeilleure.CodeGen.Arm64 ValidateBinOp(dest, src1, src2); - Debug.Assert(dest.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger); context.Assembler.Orr(dest, src1, src2); } @@ -336,7 +336,7 @@ namespace ARMeilleure.CodeGen.Arm64 ValidateUnOp(dest, source); - Debug.Assert(dest.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger); context.Assembler.Rev(dest, source); } @@ -428,7 +428,7 @@ namespace ARMeilleure.CodeGen.Arm64 EnsureSameType(src1, src2); - Debug.Assert(src1.Type.IsInteger()); + Debug.Assert(src1.Type.IsInteger); context.Assembler.Cmp(src1, src2); } @@ -442,7 +442,7 @@ namespace ARMeilleure.CodeGen.Arm64 EnsureSameType(dest, src2, src3); - Debug.Assert(dest.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger); Debug.Assert(src1.Type == OperandType.I32); context.Assembler.Cmp(src1, Const(src1.Type, 0)); @@ -468,7 +468,7 @@ namespace ARMeilleure.CodeGen.Arm64 Debug.Assert(dest.Type != source.Type); Debug.Assert(source.Type != OperandType.V128); - if (source.Type.IsInteger()) + if (source.Type.IsInteger) { context.Assembler.ScvtfScalar(dest, source); } @@ -485,7 +485,7 @@ namespace ARMeilleure.CodeGen.Arm64 Debug.Assert(dest.Type is OperandType.FP32 or OperandType.FP64); Debug.Assert(dest.Type != source.Type); - Debug.Assert(source.Type.IsInteger()); + Debug.Assert(source.Type.IsInteger); context.Assembler.UcvtfScalar(dest, source); } @@ -497,7 +497,7 @@ namespace ARMeilleure.CodeGen.Arm64 EnsureSameType(dest, source); - Debug.Assert(dest.Type.IsInteger() || source.Kind != OperandKind.Constant); + Debug.Assert(dest.Type.IsInteger || source.Kind != OperandKind.Constant); // Moves to the same register are useless. if (dest.Kind == source.Kind && dest.Value == source.Value) @@ -529,7 +529,7 @@ namespace ARMeilleure.CodeGen.Arm64 EnsureSameType(dest, source); - Debug.Assert(dest.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger); context.Assembler.Clz(dest, source); } @@ -542,7 +542,7 @@ namespace ARMeilleure.CodeGen.Arm64 ValidateBinOp(dest, dividend, divisor); - if (dest.Type.IsInteger()) + if (dest.Type.IsInteger) { context.Assembler.Sdiv(dest, dividend, divisor); } @@ -576,7 +576,7 @@ namespace ARMeilleure.CodeGen.Arm64 Operand value = operation.Destination; Operand address = operation.GetSource(0); - Debug.Assert(value.Type.IsInteger()); + Debug.Assert(value.Type.IsInteger); context.Assembler.LdrhRiUn(value, address, 0); } @@ -586,7 +586,7 @@ namespace ARMeilleure.CodeGen.Arm64 Operand value = operation.Destination; Operand address = operation.GetSource(0); - Debug.Assert(value.Type.IsInteger()); + Debug.Assert(value.Type.IsInteger); context.Assembler.LdrbRiUn(value, address, 0); } @@ -604,7 +604,7 @@ namespace ARMeilleure.CodeGen.Arm64 EnsureSameType(dest, src1, src2); - if (dest.Type.IsInteger()) + if (dest.Type.IsInteger) { context.Assembler.Mul(dest, src1, src2); } @@ -647,7 +647,7 @@ namespace ARMeilleure.CodeGen.Arm64 ValidateUnOp(dest, source); - if (dest.Type.IsInteger()) + if (dest.Type.IsInteger) { context.Assembler.Neg(dest, source); } @@ -732,7 +732,7 @@ namespace ARMeilleure.CodeGen.Arm64 Operand dest = operation.Destination; Operand source = operation.GetSource(0); - Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger && source.Type.IsInteger); context.Assembler.Sxth(dest, source); } @@ -742,7 +742,7 @@ namespace ARMeilleure.CodeGen.Arm64 Operand dest = operation.Destination; Operand source = operation.GetSource(0); - Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger && source.Type.IsInteger); context.Assembler.Sxtw(dest, source); } @@ -752,7 +752,7 @@ namespace ARMeilleure.CodeGen.Arm64 Operand dest = operation.Destination; Operand source = operation.GetSource(0); - Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger && source.Type.IsInteger); context.Assembler.Sxtb(dest, source); } @@ -823,7 +823,7 @@ namespace ARMeilleure.CodeGen.Arm64 Operand value = operation.GetSource(1); Operand address = operation.GetSource(0); - Debug.Assert(value.Type.IsInteger()); + Debug.Assert(value.Type.IsInteger); context.Assembler.StrhRiUn(value, address, 0); } @@ -833,7 +833,7 @@ namespace ARMeilleure.CodeGen.Arm64 Operand value = operation.GetSource(1); Operand address = operation.GetSource(0); - Debug.Assert(value.Type.IsInteger()); + Debug.Assert(value.Type.IsInteger); context.Assembler.StrbRiUn(value, address, 0); } @@ -858,7 +858,7 @@ namespace ARMeilleure.CodeGen.Arm64 // ValidateBinOp(dest, src1, src2); - if (dest.Type.IsInteger()) + if (dest.Type.IsInteger) { context.Assembler.Sub(dest, src1, src2); } @@ -882,7 +882,7 @@ namespace ARMeilleure.CodeGen.Arm64 if (dest != default) { - Debug.Assert(!dest.Type.IsInteger() && source.Type.IsInteger()); + Debug.Assert(!dest.Type.IsInteger && source.Type.IsInteger); OperandType destType = source.Type == OperandType.I64 ? OperandType.FP64 : OperandType.FP32; @@ -901,9 +901,9 @@ namespace ARMeilleure.CodeGen.Arm64 byte index = src2.AsByte(); - Debug.Assert(index < OperandType.V128.GetSizeInBytes() / dest.Type.GetSizeInBytes()); + Debug.Assert(index < OperandType.V128.ByteSize / dest.Type.ByteSize); - if (dest.Type.IsInteger()) + if (dest.Type.IsInteger) { context.Assembler.Umov(dest, src1, index, dest.Type == OperandType.I64 ? 3 : 2); } @@ -959,7 +959,7 @@ namespace ARMeilleure.CodeGen.Arm64 byte index = src3.AsByte(); - if (src2.Type.IsInteger()) + if (src2.Type.IsInteger) { context.Assembler.Ins(dest, src2, index, src2.Type == OperandType.I64 ? 3 : 2); } @@ -1007,7 +1007,7 @@ namespace ARMeilleure.CodeGen.Arm64 { Operand dest = operation.Destination; - Debug.Assert(!dest.Type.IsInteger()); + Debug.Assert(!dest.Type.IsInteger); context.Assembler.CmeqVector(dest, dest, dest, 2); } @@ -1016,7 +1016,7 @@ namespace ARMeilleure.CodeGen.Arm64 { Operand dest = operation.Destination; - Debug.Assert(!dest.Type.IsInteger()); + Debug.Assert(!dest.Type.IsInteger); context.Assembler.EorVector(dest, dest, dest); } @@ -1046,7 +1046,7 @@ namespace ARMeilleure.CodeGen.Arm64 Operand dest = operation.Destination; Operand source = operation.GetSource(0); - Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger && source.Type.IsInteger); context.Assembler.Uxth(dest, source); } @@ -1056,7 +1056,7 @@ namespace ARMeilleure.CodeGen.Arm64 Operand dest = operation.Destination; Operand source = operation.GetSource(0); - Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger && source.Type.IsInteger); // We can eliminate the move if source is already 32-bit and the registers are the same. if (dest.Value == source.Value && source.Type == OperandType.I32) @@ -1072,7 +1072,7 @@ namespace ARMeilleure.CodeGen.Arm64 Operand dest = operation.Destination; Operand source = operation.GetSource(0); - Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger && source.Type.IsInteger); context.Assembler.Uxtb(dest, source); } @@ -1169,7 +1169,7 @@ namespace ARMeilleure.CodeGen.Arm64 context.Assembler.StrRiPre(Register(reg, type), Register(SpRegister), -calleeSaveRegionSize); } - offset += type.GetSizeInBytes(); + offset += type.ByteSize; } while (mask != 0) @@ -1195,7 +1195,7 @@ namespace ARMeilleure.CodeGen.Arm64 context.Assembler.StpRiPre(Register(reg, type), Register(reg2, type), Register(SpRegister), -calleeSaveRegionSize); } - offset += type.GetSizeInBytes() * 2; + offset += type.ByteSize * 2; } } @@ -1273,7 +1273,7 @@ namespace ARMeilleure.CodeGen.Arm64 mask &= ~(1 << reg2); - offset -= type.GetSizeInBytes() * 2; + offset -= type.ByteSize * 2; if (offset != 0) { @@ -1286,7 +1286,7 @@ namespace ARMeilleure.CodeGen.Arm64 } else { - offset -= type.GetSizeInBytes(); + offset -= type.ByteSize; if (offset != 0) { @@ -1435,12 +1435,12 @@ namespace ARMeilleure.CodeGen.Arm64 OperandType valueType = GetMemOpValueType(currentOp); - if (valueType != GetMemOpValueType(nextOp) || op1Offset + valueType.GetSizeInBytes() != op2Offset) + if (valueType != GetMemOpValueType(nextOp) || op1Offset + valueType.ByteSize != op2Offset) { return false; } - if (!CodeGenCommon.ConstFitsOnSImm7(op1Offset, valueType.GetSizeInBytesLog2())) + if (!CodeGenCommon.ConstFitsOnSImm7(op1Offset, valueType.ByteSizeLog2)) { return false; } @@ -1549,7 +1549,7 @@ namespace ARMeilleure.CodeGen.Arm64 // EnsureSameReg (dest, src1); EnsureSameType(dest, src1); - Debug.Assert(dest.Type.IsInteger() && src2.Type == OperandType.I32); + Debug.Assert(dest.Type.IsInteger && src2.Type == OperandType.I32); } private static void EnsureSameReg(Operand op1, Operand op2) diff --git a/src/ARMeilleure/CodeGen/Arm64/CodeGeneratorIntrinsic.cs b/src/ARMeilleure/CodeGen/Arm64/CodeGeneratorIntrinsic.cs index 390dc5b2e..e7871289b 100644 --- a/src/ARMeilleure/CodeGen/Arm64/CodeGeneratorIntrinsic.cs +++ b/src/ARMeilleure/CodeGen/Arm64/CodeGeneratorIntrinsic.cs @@ -462,7 +462,7 @@ namespace ARMeilleure.CodeGen.Arm64 { instruction |= (sz << 22); - if (rd.Type.IsInteger()) + if (rd.Type.IsInteger) { context.Assembler.WriteInstructionAuto(instruction, rd, rn); } @@ -490,7 +490,7 @@ namespace ARMeilleure.CodeGen.Arm64 instruction |= (sz << 22); instruction |= (64 - fBits) << 10; - if (rd.Type.IsInteger()) + if (rd.Type.IsInteger) { Debug.Assert(rd.Type != OperandType.I32 || fBits <= 32); diff --git a/src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs b/src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs index 76a231d6c..d52aba162 100644 --- a/src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs +++ b/src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs @@ -112,7 +112,7 @@ namespace ARMeilleure.CodeGen.Arm64 if (src1.Kind == OperandKind.Constant) { - if (!src1.Type.IsInteger()) + if (!src1.Type.IsInteger) { // Handle non-integer types (FP32, FP64 and V128). // For instructions without an immediate operand, we do the following: @@ -161,7 +161,7 @@ namespace ARMeilleure.CodeGen.Arm64 if (src2.Kind == OperandKind.Constant) { - if (!src2.Type.IsInteger()) + if (!src2.Type.IsInteger) { src2 = AddFloatConstantCopy(constants, nodes, node, src2); @@ -191,7 +191,7 @@ namespace ARMeilleure.CodeGen.Arm64 if (src.Kind == OperandKind.Constant) { - if (!src.Type.IsInteger()) + if (!src.Type.IsInteger) { src = AddFloatConstantCopy(constants, nodes, node, src); @@ -282,7 +282,7 @@ namespace ARMeilleure.CodeGen.Arm64 bool passOnReg; - if (source.Type.IsInteger()) + if (source.Type.IsInteger) { passOnReg = intCount < intMax; } @@ -309,7 +309,7 @@ namespace ARMeilleure.CodeGen.Arm64 if (passOnReg) { - Operand argReg = source.Type.IsInteger() + Operand argReg = source.Type.IsInteger ? Gpr(CallingConvention.GetIntArgumentRegister(intCount++), source.Type) : Xmm(CallingConvention.GetVecArgumentRegister(vecCount++), source.Type); @@ -327,7 +327,7 @@ namespace ARMeilleure.CodeGen.Arm64 InsertConstantRegCopies(constants, nodes, nodes.AddBefore(node, spillOp)); - stackOffset += source.Type.GetSizeInBytes(); + stackOffset += source.Type.ByteSize; } } @@ -345,7 +345,7 @@ namespace ARMeilleure.CodeGen.Arm64 } else { - Operand retReg = dest.Type.IsInteger() + Operand retReg = dest.Type.IsInteger ? Gpr(CallingConvention.GetIntReturnRegister(), dest.Type) : Xmm(CallingConvention.GetVecReturnRegister(), dest.Type); @@ -385,7 +385,7 @@ namespace ARMeilleure.CodeGen.Arm64 bool passOnReg; - if (source.Type.IsInteger()) + if (source.Type.IsInteger) { passOnReg = intCount + 1 < intMax; } @@ -408,7 +408,7 @@ namespace ARMeilleure.CodeGen.Arm64 if (passOnReg) { - Operand argReg = source.Type.IsInteger() + Operand argReg = source.Type.IsInteger ? Gpr(CallingConvention.GetIntArgumentRegister(intCount++), source.Type) : Xmm(CallingConvention.GetVecArgumentRegister(vecCount++), source.Type); @@ -521,7 +521,7 @@ namespace ARMeilleure.CodeGen.Arm64 } else { - Operand retReg = source.Type.IsInteger() + Operand retReg = source.Type.IsInteger ? Gpr(CallingConvention.GetIntReturnRegister(), source.Type) : Xmm(CallingConvention.GetVecReturnRegister(), source.Type); @@ -551,7 +551,7 @@ namespace ARMeilleure.CodeGen.Arm64 { OperandType argType = cctx.FuncArgTypes[cIndex]; - if (argType.IsInteger()) + if (argType.IsInteger) { intCount++; } @@ -567,7 +567,7 @@ namespace ARMeilleure.CodeGen.Arm64 bool passOnReg; - if (source.Type.IsInteger()) + if (source.Type.IsInteger) { passOnReg = intCount < CallingConvention.GetArgumentsOnRegsCount(); } @@ -606,7 +606,7 @@ namespace ARMeilleure.CodeGen.Arm64 { Operand pArg = Local(dest.Type); - Operand argReg = dest.Type.IsInteger() + Operand argReg = dest.Type.IsInteger ? Gpr(CallingConvention.GetIntArgumentRegister(intCount), dest.Type) : Xmm(CallingConvention.GetVecArgumentRegister(vecCount), dest.Type); diff --git a/src/ARMeilleure/CodeGen/Optimizations/Simplification.cs b/src/ARMeilleure/CodeGen/Optimizations/Simplification.cs index 53a7f3ede..a80b4adad 100644 --- a/src/ARMeilleure/CodeGen/Optimizations/Simplification.cs +++ b/src/ARMeilleure/CodeGen/Optimizations/Simplification.cs @@ -105,7 +105,7 @@ namespace ARMeilleure.CodeGen.Optimizations Operand x = operation.GetSource(0); Operand y = operation.GetSource(1); - if (x == y && x.Type.IsInteger()) + if (x == y && x.Type.IsInteger) { operation.TurnIntoCopy(Const(x.Type, 0)); } @@ -161,7 +161,7 @@ namespace ARMeilleure.CodeGen.Optimizations private static bool IsConstEqual(Operand operand, ulong comparand) { - if (operand.Kind != OperandKind.Constant || !operand.Type.IsInteger()) + if (operand.Kind != OperandKind.Constant || !operand.Type.IsInteger) { return false; } diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/CopyResolver.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/CopyResolver.cs index 8b135afab..574de4cd6 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/CopyResolver.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/CopyResolver.cs @@ -98,7 +98,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators { OperandType type = types[copyDest]; - type = type.IsInteger() ? OperandType.I64 : OperandType.V128; + type = type.IsInteger ? OperandType.I64 : OperandType.V128; EmitXorSwap(sequence, GetRegister(copyDest, type), GetRegister(copySource, type)); diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs index 5f1d6ce89..1e9aee5fd 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs @@ -178,7 +178,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators } else if (dest.Kind == OperandKind.Register) { - if (dest.Type.IsInteger()) + if (dest.Type.IsInteger) { intFixedRegisters |= 1 << dest.GetRegister().Index; } @@ -236,7 +236,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators { Register reg = info.Register.GetRegister(); - if (local.Type.IsInteger()) + if (local.Type.IsInteger) { intLocalFreeRegisters |= 1 << reg.Index; } @@ -254,7 +254,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators if (temp == default || info.Sequence != sequence) { - temp = local.Type.IsInteger() + temp = local.Type.IsInteger ? GetSpillTemp(local, intSpillTempRegisters, ref intLocalUse) : GetSpillTemp(local, vecSpillTempRegisters, ref vecLocalUse); @@ -335,7 +335,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators if (info.UsesAllocated == 0) { - int mask = dest.Type.IsInteger() + int mask = dest.Type.IsInteger ? intLocalFreeRegisters : vecLocalFreeRegisters; @@ -343,9 +343,9 @@ namespace ARMeilleure.CodeGen.RegisterAllocators { int selectedReg = BitOperations.TrailingZeroCount(mask); - info.Register = Register(selectedReg, info.Type.ToRegisterType(), info.Type); + info.Register = Register(selectedReg, info.Type.Register, info.Type); - if (dest.Type.IsInteger()) + if (dest.Type.IsInteger) { intLocalFreeRegisters &= ~(1 << selectedReg); intUsedRegisters |= 1 << selectedReg; @@ -359,7 +359,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators else { info.Register = default; - info.SpillOffset = Const(stackAlloc.Allocate(dest.Type.GetSizeInBytes())); + info.SpillOffset = Const(stackAlloc.Allocate(dest.Type.ByteSize)); } } @@ -377,7 +377,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators if (temp == default || info.Sequence != sequence) { - temp = dest.Type.IsInteger() + temp = dest.Type.IsInteger ? GetSpillTemp(dest, intSpillTempRegisters, ref intLocalAsg) : GetSpillTemp(dest, vecSpillTempRegisters, ref vecLocalAsg); @@ -443,7 +443,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators useMask |= 1 << selectedReg; - return Register(selectedReg, local.Type.ToRegisterType(), local.Type); + return Register(selectedReg, local.Type.Register, local.Type); } private static int UsesCount(Operand local) diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/LinearScanAllocator.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/LinearScanAllocator.cs index 92fedf7bf..94883b39b 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/LinearScanAllocator.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/LinearScanAllocator.cs @@ -208,7 +208,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators private bool TryAllocateRegWithoutSpill(AllocationContext context, LiveInterval current, int cIndex, int registersCount) { - RegisterType regType = current.Local.Type.ToRegisterType(); + RegisterType regType = current.Local.Type.Register; Span freePositions = stackalloc int[registersCount]; @@ -318,7 +318,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators private void AllocateRegWithSpill(AllocationContext context, LiveInterval current, int cIndex, int registersCount) { - RegisterType regType = current.Local.Type.ToRegisterType(); + RegisterType regType = current.Local.Type.Register; Span usePositions = stackalloc int[registersCount]; Span blockedPositions = stackalloc int[registersCount]; diff --git a/src/ARMeilleure/CodeGen/RegisterAllocators/StackAllocator.cs b/src/ARMeilleure/CodeGen/RegisterAllocators/StackAllocator.cs index 13995bc8d..b89034609 100644 --- a/src/ARMeilleure/CodeGen/RegisterAllocators/StackAllocator.cs +++ b/src/ARMeilleure/CodeGen/RegisterAllocators/StackAllocator.cs @@ -10,7 +10,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators public int Allocate(OperandType type) { - return Allocate(type.GetSizeInBytes()); + return Allocate(type.ByteSize); } public int Allocate(int sizeInBytes) diff --git a/src/ARMeilleure/CodeGen/X86/Assembler.cs b/src/ARMeilleure/CodeGen/X86/Assembler.cs index c27ee43cb..d1826a4fb 100644 --- a/src/ARMeilleure/CodeGen/X86/Assembler.cs +++ b/src/ARMeilleure/CodeGen/X86/Assembler.cs @@ -385,7 +385,7 @@ namespace ARMeilleure.CodeGen.X86 { ref readonly InstructionInfo info = ref _instTable[(int)X86Instruction.Movd]; - if (source.Type.IsInteger() || source.Kind == OperandKind.Memory) + if (source.Type.IsInteger || source.Kind == OperandKind.Memory) { WriteOpCode(dest, default, source, OperandType.None, info.Flags, info.OpRRM, rrm: true); } @@ -416,11 +416,11 @@ namespace ARMeilleure.CodeGen.X86 InstructionFlags flags = info.Flags | InstructionFlags.RexW; - if (source.Type.IsInteger() || source.Kind == OperandKind.Memory) + if (source.Type.IsInteger || source.Kind == OperandKind.Memory) { WriteOpCode(dest, default, source, OperandType.None, flags, info.OpRRM, rrm: true); } - else if (dest.Type.IsInteger() || dest.Kind == OperandKind.Memory) + else if (dest.Type.IsInteger || dest.Kind == OperandKind.Memory) { WriteOpCode(dest, default, source, OperandType.None, flags, info.OpRMR); } diff --git a/src/ARMeilleure/CodeGen/X86/CodeGenerator.cs b/src/ARMeilleure/CodeGen/X86/CodeGenerator.cs index b7e18a263..ed425f476 100644 --- a/src/ARMeilleure/CodeGen/X86/CodeGenerator.cs +++ b/src/ARMeilleure/CodeGen/X86/CodeGenerator.cs @@ -289,7 +289,7 @@ namespace ARMeilleure.CodeGen.X86 EnsureSameType(dest, source); - Debug.Assert(dest.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger); context.Assembler.Popcnt(dest, source, dest.Type); @@ -303,7 +303,7 @@ namespace ARMeilleure.CodeGen.X86 EnsureSameType(dest, source); - Debug.Assert(!dest.Type.IsInteger()); + Debug.Assert(!dest.Type.IsInteger); context.Assembler.WriteInstruction(info.Inst, dest, source); @@ -315,7 +315,7 @@ namespace ARMeilleure.CodeGen.X86 Operand dest = operation.Destination; Operand source = operation.GetSource(0); - Debug.Assert(dest.Type.IsInteger() && !source.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger && !source.Type.IsInteger); if (operation.Intrinsic == Intrinsic.X86Cvtsi2si) { @@ -349,8 +349,8 @@ namespace ARMeilleure.CodeGen.X86 EnsureSameReg(dest, src1); } - Debug.Assert(!dest.Type.IsInteger()); - Debug.Assert(!src2.Type.IsInteger() || src2.Kind == OperandKind.Constant); + Debug.Assert(!dest.Type.IsInteger); + Debug.Assert(!src2.Type.IsInteger || src2.Kind == OperandKind.Constant); context.Assembler.WriteInstruction(info.Inst, dest, src1, src2); @@ -370,7 +370,7 @@ namespace ARMeilleure.CodeGen.X86 EnsureSameReg(dest, src1); } - Debug.Assert(!dest.Type.IsInteger() && src2.Type.IsInteger()); + Debug.Assert(!dest.Type.IsInteger && src2.Type.IsInteger); context.Assembler.WriteInstruction(info.Inst, dest, src1, src2, src2.Type); @@ -385,7 +385,7 @@ namespace ARMeilleure.CodeGen.X86 EnsureSameReg(dest, src1); - Debug.Assert(dest.Type.IsInteger() && src1.Type.IsInteger() && src2.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger && src1.Type.IsInteger && src2.Type.IsInteger); context.Assembler.WriteInstruction(info.Inst, dest, src2, dest.Type); @@ -405,7 +405,7 @@ namespace ARMeilleure.CodeGen.X86 EnsureSameReg(dest, src1); } - Debug.Assert(!dest.Type.IsInteger() && src2.Kind == OperandKind.Constant); + Debug.Assert(!dest.Type.IsInteger && src2.Kind == OperandKind.Constant); context.Assembler.WriteInstruction(info.Inst, dest, src1, src2.AsByte()); @@ -421,7 +421,7 @@ namespace ARMeilleure.CodeGen.X86 EnsureSameType(dest, src1, src2, src3); - Debug.Assert(!dest.Type.IsInteger()); + Debug.Assert(!dest.Type.IsInteger); if (info.Inst == X86Instruction.Blendvpd && HardwareCapabilities.SupportsVexEncoding) { @@ -461,7 +461,7 @@ namespace ARMeilleure.CodeGen.X86 EnsureSameReg(dest, src1); } - Debug.Assert(!dest.Type.IsInteger() && src3.Kind == OperandKind.Constant); + Debug.Assert(!dest.Type.IsInteger && src3.Kind == OperandKind.Constant); context.Assembler.WriteInstruction(info.Inst, dest, src1, src2, src3.AsByte()); @@ -512,7 +512,7 @@ namespace ARMeilleure.CodeGen.X86 Operand src1 = operation.GetSource(0); Operand src2 = operation.GetSource(1); - if (dest.Type.IsInteger()) + if (dest.Type.IsInteger) { // If Destination and Source 1 Operands are the same, perform a standard add as there are no benefits to using LEA. if (dest.Kind == src1.Kind && dest.Value == src1.Value) @@ -567,7 +567,7 @@ namespace ARMeilleure.CodeGen.X86 ValidateBinOp(dest, src1, src2); - Debug.Assert(dest.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger); // Note: GenerateCompareCommon makes the assumption that BitwiseAnd will emit only a single `and` // instruction. @@ -582,7 +582,7 @@ namespace ARMeilleure.CodeGen.X86 ValidateBinOp(dest, src1, src2); - if (dest.Type.IsInteger()) + if (dest.Type.IsInteger) { context.Assembler.Xor(dest, src2, dest.Type); } @@ -599,7 +599,7 @@ namespace ARMeilleure.CodeGen.X86 ValidateUnOp(dest, source); - Debug.Assert(dest.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger); context.Assembler.Not(dest); } @@ -612,7 +612,7 @@ namespace ARMeilleure.CodeGen.X86 ValidateBinOp(dest, src1, src2); - Debug.Assert(dest.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger); context.Assembler.Or(dest, src2, dest.Type); } @@ -637,7 +637,7 @@ namespace ARMeilleure.CodeGen.X86 ValidateUnOp(dest, source); - Debug.Assert(dest.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger); context.Assembler.Bswap(dest); } @@ -676,7 +676,7 @@ namespace ARMeilleure.CodeGen.X86 EnsureSameType(src1, src2); - Debug.Assert(src1.Type.IsInteger()); + Debug.Assert(src1.Type.IsInteger); if (src2.Kind == OperandKind.Constant && src2.Value == 0) { @@ -766,7 +766,7 @@ namespace ARMeilleure.CodeGen.X86 EnsureSameReg(dest, src3); EnsureSameType(dest, src2, src3); - Debug.Assert(dest.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger); Debug.Assert(src1.Type == OperandType.I32); context.Assembler.Test(src1, src1, src1.Type); @@ -792,9 +792,9 @@ namespace ARMeilleure.CodeGen.X86 if (dest.Type == OperandType.FP32) { - Debug.Assert(source.Type.IsInteger() || source.Type == OperandType.FP64); + Debug.Assert(source.Type.IsInteger || source.Type == OperandType.FP64); - if (source.Type.IsInteger()) + if (source.Type.IsInteger) { context.Assembler.Xorps(dest, dest, dest); context.Assembler.Cvtsi2ss(dest, dest, source, source.Type); @@ -808,9 +808,9 @@ namespace ARMeilleure.CodeGen.X86 } else /* if (dest.Type == OperandType.FP64) */ { - Debug.Assert(source.Type.IsInteger() || source.Type == OperandType.FP32); + Debug.Assert(source.Type.IsInteger || source.Type == OperandType.FP32); - if (source.Type.IsInteger()) + if (source.Type.IsInteger) { context.Assembler.Xorps(dest, dest, dest); context.Assembler.Cvtsi2sd(dest, dest, source, source.Type); @@ -831,7 +831,7 @@ namespace ARMeilleure.CodeGen.X86 EnsureSameType(dest, source); - Debug.Assert(dest.Type.IsInteger() || source.Kind != OperandKind.Constant); + Debug.Assert(dest.Type.IsInteger || source.Kind != OperandKind.Constant); // Moves to the same register are useless. if (dest.Kind == source.Kind && dest.Value == source.Value) @@ -845,7 +845,7 @@ namespace ARMeilleure.CodeGen.X86 // Assemble "mov reg, 0" as "xor reg, reg" as the later is more efficient. context.Assembler.Xor(dest, dest, OperandType.I32); } - else if (dest.Type.IsInteger()) + else if (dest.Type.IsInteger) { context.Assembler.Mov(dest, source, dest.Type); } @@ -862,7 +862,7 @@ namespace ARMeilleure.CodeGen.X86 EnsureSameType(dest, source); - Debug.Assert(dest.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger); context.Assembler.Bsr(dest, source, dest.Type); @@ -894,12 +894,12 @@ namespace ARMeilleure.CodeGen.X86 Operand dividend = operation.GetSource(0); Operand divisor = operation.GetSource(1); - if (!dest.Type.IsInteger()) + if (!dest.Type.IsInteger) { ValidateBinOp(dest, dividend, divisor); } - if (dest.Type.IsInteger()) + if (dest.Type.IsInteger) { divisor = operation.GetSource(2); @@ -932,7 +932,7 @@ namespace ARMeilleure.CodeGen.X86 Operand rdx = Register(X86Register.Rdx); - Debug.Assert(divisor.Type.IsInteger()); + Debug.Assert(divisor.Type.IsInteger); context.Assembler.Xor(rdx, rdx, OperandType.I32); context.Assembler.Div(divisor); @@ -967,7 +967,7 @@ namespace ARMeilleure.CodeGen.X86 Operand value = operation.Destination; Operand address = Memory(operation.GetSource(0), value.Type); - Debug.Assert(value.Type.IsInteger()); + Debug.Assert(value.Type.IsInteger); context.Assembler.Movzx16(value, address, value.Type); } @@ -977,7 +977,7 @@ namespace ARMeilleure.CodeGen.X86 Operand value = operation.Destination; Operand address = Memory(operation.GetSource(0), value.Type); - Debug.Assert(value.Type.IsInteger()); + Debug.Assert(value.Type.IsInteger); context.Assembler.Movzx8(value, address, value.Type); } @@ -1000,7 +1000,7 @@ namespace ARMeilleure.CodeGen.X86 EnsureSameType(dest, src1, src2); - if (dest.Type.IsInteger()) + if (dest.Type.IsInteger) { if (src2.Kind == OperandKind.Constant) { @@ -1046,7 +1046,7 @@ namespace ARMeilleure.CodeGen.X86 ValidateUnOp(dest, source); - Debug.Assert(dest.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger); context.Assembler.Neg(dest); } @@ -1107,7 +1107,7 @@ namespace ARMeilleure.CodeGen.X86 Operand dest = operation.Destination; Operand source = operation.GetSource(0); - Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger && source.Type.IsInteger); context.Assembler.Movsx16(dest, source, dest.Type); } @@ -1117,7 +1117,7 @@ namespace ARMeilleure.CodeGen.X86 Operand dest = operation.Destination; Operand source = operation.GetSource(0); - Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger && source.Type.IsInteger); context.Assembler.Movsx32(dest, source, dest.Type); } @@ -1127,7 +1127,7 @@ namespace ARMeilleure.CodeGen.X86 Operand dest = operation.Destination; Operand source = operation.GetSource(0); - Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger && source.Type.IsInteger); context.Assembler.Movsx8(dest, source, dest.Type); } @@ -1187,7 +1187,7 @@ namespace ARMeilleure.CodeGen.X86 Operand value = operation.GetSource(1); Operand address = Memory(operation.GetSource(0), value.Type); - Debug.Assert(value.Type.IsInteger()); + Debug.Assert(value.Type.IsInteger); context.Assembler.Mov16(address, value); } @@ -1197,7 +1197,7 @@ namespace ARMeilleure.CodeGen.X86 Operand value = operation.GetSource(1); Operand address = Memory(operation.GetSource(0), value.Type); - Debug.Assert(value.Type.IsInteger()); + Debug.Assert(value.Type.IsInteger); context.Assembler.Mov8(address, value); } @@ -1210,7 +1210,7 @@ namespace ARMeilleure.CodeGen.X86 ValidateBinOp(dest, src1, src2); - if (dest.Type.IsInteger()) + if (dest.Type.IsInteger) { context.Assembler.Sub(dest, src2, dest.Type); } @@ -1236,7 +1236,7 @@ namespace ARMeilleure.CodeGen.X86 Operand dest = operation.Destination; Operand source = operation.GetSource(0); - Debug.Assert(!dest.Type.IsInteger() && source.Type.IsInteger()); + Debug.Assert(!dest.Type.IsInteger && source.Type.IsInteger); if (source.Type == OperandType.I32) { @@ -1259,7 +1259,7 @@ namespace ARMeilleure.CodeGen.X86 byte index = src2.AsByte(); - Debug.Assert(index < OperandType.V128.GetSizeInBytes() / dest.Type.GetSizeInBytes()); + Debug.Assert(index < OperandType.V128.ByteSize / dest.Type.ByteSize); if (dest.Type == OperandType.I32) { @@ -1541,7 +1541,7 @@ namespace ARMeilleure.CodeGen.X86 { Operand dest = operation.Destination; - Debug.Assert(!dest.Type.IsInteger()); + Debug.Assert(!dest.Type.IsInteger); context.Assembler.Pcmpeqw(dest, dest, dest); } @@ -1550,7 +1550,7 @@ namespace ARMeilleure.CodeGen.X86 { Operand dest = operation.Destination; - Debug.Assert(!dest.Type.IsInteger()); + Debug.Assert(!dest.Type.IsInteger); context.Assembler.Xorps(dest, dest, dest); } @@ -1580,7 +1580,7 @@ namespace ARMeilleure.CodeGen.X86 Operand dest = operation.Destination; Operand source = operation.GetSource(0); - Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger && source.Type.IsInteger); context.Assembler.Movzx16(dest, source, OperandType.I32); } @@ -1590,7 +1590,7 @@ namespace ARMeilleure.CodeGen.X86 Operand dest = operation.Destination; Operand source = operation.GetSource(0); - Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger && source.Type.IsInteger); // We can eliminate the move if source is already 32-bit and the registers are the same. if (dest.Value == source.Value && source.Type == OperandType.I32) @@ -1606,7 +1606,7 @@ namespace ARMeilleure.CodeGen.X86 Operand dest = operation.Destination; Operand source = operation.GetSource(0); - Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger()); + Debug.Assert(dest.Type.IsInteger && source.Type.IsInteger); context.Assembler.Movzx8(dest, source, OperandType.I32); } @@ -1713,12 +1713,12 @@ namespace ARMeilleure.CodeGen.X86 EnsureSameReg(dest, src1); EnsureSameType(dest, src1); - Debug.Assert(dest.Type.IsInteger() && src2.Type == OperandType.I32); + Debug.Assert(dest.Type.IsInteger && src2.Type == OperandType.I32); } private static void EnsureSameReg(Operand op1, Operand op2) { - if (!op1.Type.IsInteger() && HardwareCapabilities.SupportsVexEncoding) + if (!op1.Type.IsInteger && HardwareCapabilities.SupportsVexEncoding) { return; } diff --git a/src/ARMeilleure/CodeGen/X86/PreAllocator.cs b/src/ARMeilleure/CodeGen/X86/PreAllocator.cs index 6b93efdfb..d3bc6be6a 100644 --- a/src/ARMeilleure/CodeGen/X86/PreAllocator.cs +++ b/src/ARMeilleure/CodeGen/X86/PreAllocator.cs @@ -86,7 +86,7 @@ namespace ARMeilleure.CodeGen.X86 break; case Instruction.Negate: - if (!node.GetSource(0).Type.IsInteger()) + if (!node.GetSource(0).Type.IsInteger) { GenerateNegate(block.Operations, node); } @@ -159,7 +159,7 @@ namespace ARMeilleure.CodeGen.X86 if (src1.Kind == OperandKind.Constant) { - if (!src1.Type.IsInteger()) + if (!src1.Type.IsInteger) { // Handle non-integer types (FP32, FP64 and V128). // For instructions without an immediate operand, we do the following: @@ -208,7 +208,7 @@ namespace ARMeilleure.CodeGen.X86 if (src2.Kind == OperandKind.Constant) { - if (!src2.Type.IsInteger()) + if (!src2.Type.IsInteger) { src2 = AddXmmCopy(nodes, node, src2); @@ -298,7 +298,7 @@ namespace ARMeilleure.CodeGen.X86 // - The dividend is always in RDX:RAX. // - The result is always in RAX. // - Additionally it also writes the remainder in RDX. - if (dest.Type.IsInteger()) + if (dest.Type.IsInteger) { Operand src1 = node.GetSource(0); @@ -466,7 +466,7 @@ namespace ARMeilleure.CodeGen.X86 Operand dest = node.Destination; Operand source = node.GetSource(0); - Debug.Assert(source.Type.IsInteger(), $"Invalid source type \"{source.Type}\"."); + Debug.Assert(source.Type.IsInteger, $"Invalid source type \"{source.Type}\"."); Operation currentNode = node; @@ -654,10 +654,10 @@ namespace ARMeilleure.CodeGen.X86 switch (operation.Instruction) { case Instruction.Add: - return !HardwareCapabilities.SupportsVexEncoding && !operation.Destination.Type.IsInteger(); + return !HardwareCapabilities.SupportsVexEncoding && !operation.Destination.Type.IsInteger; case Instruction.Multiply: case Instruction.Subtract: - return !HardwareCapabilities.SupportsVexEncoding || operation.Destination.Type.IsInteger(); + return !HardwareCapabilities.SupportsVexEncoding || operation.Destination.Type.IsInteger; case Instruction.BitwiseAnd: case Instruction.BitwiseExclusiveOr: @@ -672,7 +672,7 @@ namespace ARMeilleure.CodeGen.X86 return true; case Instruction.Divide: - return !HardwareCapabilities.SupportsVexEncoding && !operation.Destination.Type.IsInteger(); + return !HardwareCapabilities.SupportsVexEncoding && !operation.Destination.Type.IsInteger; case Instruction.VectorInsert: case Instruction.VectorInsert16: diff --git a/src/ARMeilleure/CodeGen/X86/PreAllocatorSystemV.cs b/src/ARMeilleure/CodeGen/X86/PreAllocatorSystemV.cs index cff1c7240..368c53789 100644 --- a/src/ARMeilleure/CodeGen/X86/PreAllocatorSystemV.cs +++ b/src/ARMeilleure/CodeGen/X86/PreAllocatorSystemV.cs @@ -35,7 +35,7 @@ namespace ARMeilleure.CodeGen.X86 bool passOnReg; - if (source.Type.IsInteger()) + if (source.Type.IsInteger) { passOnReg = intCount < intMax; } @@ -62,7 +62,7 @@ namespace ARMeilleure.CodeGen.X86 if (passOnReg) { - Operand argReg = source.Type.IsInteger() + Operand argReg = source.Type.IsInteger ? Gpr(CallingConvention.GetIntArgumentRegister(intCount++), source.Type) : Xmm(CallingConvention.GetVecArgumentRegister(vecCount++), source.Type); @@ -80,7 +80,7 @@ namespace ARMeilleure.CodeGen.X86 InsertConstantRegCopies(nodes, nodes.AddBefore(node, spillOp)); - stackOffset += source.Type.GetSizeInBytes(); + stackOffset += source.Type.ByteSize; } } @@ -102,7 +102,7 @@ namespace ARMeilleure.CodeGen.X86 } else { - Operand retReg = dest.Type.IsInteger() + Operand retReg = dest.Type.IsInteger ? Gpr(CallingConvention.GetIntReturnRegister(), dest.Type) : Xmm(CallingConvention.GetVecReturnRegister(), dest.Type); @@ -137,7 +137,7 @@ namespace ARMeilleure.CodeGen.X86 bool passOnReg; - if (source.Type.IsInteger()) + if (source.Type.IsInteger) { passOnReg = intCount + 1 < intMax; } @@ -160,7 +160,7 @@ namespace ARMeilleure.CodeGen.X86 if (passOnReg) { - Operand argReg = source.Type.IsInteger() + Operand argReg = source.Type.IsInteger ? Gpr(CallingConvention.GetIntArgumentRegister(intCount++), source.Type) : Xmm(CallingConvention.GetVecArgumentRegister(vecCount++), source.Type); @@ -210,7 +210,7 @@ namespace ARMeilleure.CodeGen.X86 { OperandType argType = cctx.FuncArgTypes[cIndex]; - if (argType.IsInteger()) + if (argType.IsInteger) { intCount++; } @@ -226,7 +226,7 @@ namespace ARMeilleure.CodeGen.X86 bool passOnReg; - if (source.Type.IsInteger()) + if (source.Type.IsInteger) { passOnReg = intCount < CallingConvention.GetIntArgumentsOnRegsCount(); } @@ -265,7 +265,7 @@ namespace ARMeilleure.CodeGen.X86 { Operand pArg = Local(dest.Type); - Operand argReg = dest.Type.IsInteger() + Operand argReg = dest.Type.IsInteger ? Gpr(CallingConvention.GetIntArgumentRegister(intCount), dest.Type) : Xmm(CallingConvention.GetVecArgumentRegister(vecCount), dest.Type); @@ -320,7 +320,7 @@ namespace ARMeilleure.CodeGen.X86 } else { - Operand retReg = source.Type.IsInteger() + Operand retReg = source.Type.IsInteger ? Gpr(CallingConvention.GetIntReturnRegister(), source.Type) : Xmm(CallingConvention.GetVecReturnRegister(), source.Type); diff --git a/src/ARMeilleure/CodeGen/X86/PreAllocatorWindows.cs b/src/ARMeilleure/CodeGen/X86/PreAllocatorWindows.cs index 52f72ac69..6f4458d74 100644 --- a/src/ARMeilleure/CodeGen/X86/PreAllocatorWindows.cs +++ b/src/ARMeilleure/CodeGen/X86/PreAllocatorWindows.cs @@ -40,7 +40,7 @@ namespace ARMeilleure.CodeGen.X86 if (dest != default && dest.Type == OperandType.V128) { - int stackOffset = AllocateOnStack(dest.Type.GetSizeInBytes()); + int stackOffset = AllocateOnStack(dest.Type.ByteSize); arg0Reg = Gpr(CallingConvention.GetIntArgumentRegister(0), OperandType.I64); @@ -76,7 +76,7 @@ namespace ARMeilleure.CodeGen.X86 { Operand stackAddr = Local(OperandType.I64); - int stackOffset = AllocateOnStack(source.Type.GetSizeInBytes()); + int stackOffset = AllocateOnStack(source.Type.ByteSize); nodes.AddBefore(node, Operation(Instruction.StackAlloc, stackAddr, Const(stackOffset))); @@ -96,7 +96,7 @@ namespace ARMeilleure.CodeGen.X86 int argIndex = index + retArgs; - if (source.Type.IsInteger()) + if (source.Type.IsInteger) { argReg = Gpr(CallingConvention.GetIntArgumentRegister(argIndex), source.Type); } @@ -140,7 +140,7 @@ namespace ARMeilleure.CodeGen.X86 } else { - Operand retReg = dest.Type.IsInteger() + Operand retReg = dest.Type.IsInteger ? Gpr(CallingConvention.GetIntReturnRegister(), dest.Type) : Xmm(CallingConvention.GetVecReturnRegister(), dest.Type); @@ -171,7 +171,7 @@ namespace ARMeilleure.CodeGen.X86 for (int index = 0; index < argsCount; index++) { Operand source = node.GetSource(1 + index); - Operand argReg = source.Type.IsInteger() + Operand argReg = source.Type.IsInteger ? Gpr(CallingConvention.GetIntArgumentRegister(index), source.Type) : Xmm(CallingConvention.GetVecArgumentRegister(index), source.Type); @@ -219,7 +219,7 @@ namespace ARMeilleure.CodeGen.X86 { Operand argReg, pArg; - if (dest.Type.IsInteger()) + if (dest.Type.IsInteger) { argReg = Gpr(CallingConvention.GetIntArgumentRegister(index), dest.Type); pArg = Local(dest.Type); @@ -283,7 +283,7 @@ namespace ARMeilleure.CodeGen.X86 Operand source = node.GetSource(0); Operand retReg; - if (source.Type.IsInteger()) + if (source.Type.IsInteger) { retReg = Gpr(CallingConvention.GetIntReturnRegister(), source.Type); } diff --git a/src/ARMeilleure/Instructions/InstEmitHashHelper.cs b/src/ARMeilleure/Instructions/InstEmitHashHelper.cs index 19a607dfc..92f9c9c35 100644 --- a/src/ARMeilleure/Instructions/InstEmitHashHelper.cs +++ b/src/ARMeilleure/Instructions/InstEmitHashHelper.cs @@ -16,7 +16,7 @@ namespace ARMeilleure.Instructions public static Operand EmitCrc32(ArmEmitterContext context, Operand crc, Operand value, int size, bool castagnoli) { - Debug.Assert(crc.Type.IsInteger() && value.Type.IsInteger()); + Debug.Assert(crc.Type.IsInteger && value.Type.IsInteger); Debug.Assert(size is >= 0 and < 4); Debug.Assert((size < 3) || (value.Type == OperandType.I64)); diff --git a/src/ARMeilleure/IntermediateRepresentation/OperandType.cs b/src/ARMeilleure/IntermediateRepresentation/OperandType.cs index fec22eed6..027be8cac 100644 --- a/src/ARMeilleure/IntermediateRepresentation/OperandType.cs +++ b/src/ARMeilleure/IntermediateRepresentation/OperandType.cs @@ -14,48 +14,38 @@ namespace ARMeilleure.IntermediateRepresentation static class OperandTypeExtensions { - public static bool IsInteger(this OperandType type) + extension(OperandType type) { - return type is OperandType.I32 or - OperandType.I64; - } - - public static RegisterType ToRegisterType(this OperandType type) - { - return type switch + public bool IsInteger => type is OperandType.I32 or OperandType.I64; + + public RegisterType Register => type switch { OperandType.FP32 => RegisterType.Vector, OperandType.FP64 => RegisterType.Vector, OperandType.I32 => RegisterType.Integer, OperandType.I64 => RegisterType.Integer, OperandType.V128 => RegisterType.Vector, - _ => throw new InvalidOperationException($"Invalid operand type \"{type}\"."), + _ => throw new InvalidOperationException($"Invalid operand type \"{type}\".") }; - } - - public static int GetSizeInBytes(this OperandType type) - { - return type switch + + public int ByteSize => type switch { OperandType.FP32 => 4, OperandType.FP64 => 8, OperandType.I32 => 4, OperandType.I64 => 8, OperandType.V128 => 16, - _ => throw new InvalidOperationException($"Invalid operand type \"{type}\"."), + _ => throw new InvalidOperationException($"Invalid operand type \"{type}\".") }; - } - - public static int GetSizeInBytesLog2(this OperandType type) - { - return type switch + + public int ByteSizeLog2 => type switch { OperandType.FP32 => 2, OperandType.FP64 => 3, OperandType.I32 => 2, OperandType.I64 => 3, OperandType.V128 => 4, - _ => throw new InvalidOperationException($"Invalid operand type \"{type}\"."), + _ => throw new InvalidOperationException($"Invalid operand type \"{type}\".") }; } }