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Fix Addp_S in AOpCodeTable. Add 5 Tests: ADDP (scalar), ADDP (vector), ADDV. (#96)

Browse source 
* Update AOpCodeTable.cs

* Update Pseudocode.cs

* Update Instructions.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update Instructions.cs

* Revert "Started to work in improving the sync primitives"
This commit is contained in:
LDj3SNuD 2018-04-21 21:15:04 +02:00 • committed by gdkchan
parent 90279d96ea
commit 302c1d2861
5 changed files with 314 additions and 56 deletions
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82
Ryujinx.Tests/Cpu/Tester/Instructions.cs
View file

@ -1763,6 +1763,53 @@ namespace Ryujinx.Tests.Cpu.Tester
V(d, result);
}
// https://meriac.github.io/archex/A64_v83A_ISA/addp_advsimd_pair.xml
public static void Addp_S(Bits size, Bits Rn, Bits Rd)
{
/* Decode Scalar */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
/* if size != '11' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = esize * 2;
// int elements = 2;
ReduceOp op = ReduceOp.ReduceOp_ADD;
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits operand = V(datasize, n);
V(d, Reduce(op, operand, esize));
}
// https://meriac.github.io/archex/A64_v83A_ISA/addv_advsimd.xml
public static void Addv_V(bool Q, Bits size, Bits Rn, Bits Rd)
{
/* Decode */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
/* if size:Q == '100' then ReservedValue(); */
/* if size == '11' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = (Q ? 128 : 64);
// int elements = datasize / esize;
ReduceOp op = ReduceOp.ReduceOp_ADD;
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits operand = V(datasize, n);
V(d, Reduce(op, operand, esize));
}
// https://meriac.github.io/archex/A64_v83A_ISA/neg_advsimd.xml#NEG_asisdmisc_R
public static void Neg_S(Bits size, Bits Rn, Bits Rd)
{
@ -1995,6 +2042,41 @@ namespace Ryujinx.Tests.Cpu.Tester
Vpart(d, part, result);
}
// https://meriac.github.io/archex/A64_v83A_ISA/addp_advsimd_vec.xml
public static void Addp_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{
/* Decode Vector */
int d = (int)UInt(Rd);
int n = (int)UInt(Rn);
int m = (int)UInt(Rm);
/* if size:Q == '110' then ReservedValue(); */
int esize = 8 << (int)UInt(size);
int datasize = (Q ? 128 : 64);
int elements = datasize / esize;
/* Operation */
/* CheckFPAdvSIMDEnabled64(); */
Bits result = new Bits(datasize);
Bits operand1 = V(datasize, n);
Bits operand2 = V(datasize, m);
Bits concat = Bits.Concat(operand2, operand1);
Bits element1;
Bits element2;
for (int e = 0; e <= elements - 1; e++)
{
element1 = Elem(concat, 2 * e, esize);
element2 = Elem(concat, (2 * e) + 1, esize);
Elem(result, e, esize, element1 + element2);
}
V(d, result);
}
// https://meriac.github.io/archex/A64_v83A_ISA/raddhn_advsimd.xml
public static void Raddhn_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
{

50
Ryujinx.Tests/Cpu/Tester/Pseudocode.cs
View file

@ -442,6 +442,56 @@ namespace Ryujinx.Tests.Cpu.Tester
// #ShiftType
public enum ShiftType {ShiftType_LSL, ShiftType_LSR, ShiftType_ASR, ShiftType_ROR};
#endregion
#region "instrs/vector/reduce/reduceop/"
public static Bits Reduce(ReduceOp op, Bits input, int esize)
{
int N = input.Count;
int half;
Bits hi;
Bits lo;
Bits result = new Bits(esize);
if (N == esize)
{
return new Bits(input);
}
half = N / 2;
hi = Reduce(op, input[N - 1, half], esize);
lo = Reduce(op, input[half - 1, 0], esize);
switch (op)
{
case ReduceOp.ReduceOp_FMINNUM:
/* result = FPMinNum(lo, hi, FPCR); */
break;
case ReduceOp.ReduceOp_FMAXNUM:
/* result = FPMaxNum(lo, hi, FPCR); */
break;
case ReduceOp.ReduceOp_FMIN:
/* result = FPMin(lo, hi, FPCR); */
break;
case ReduceOp.ReduceOp_FMAX:
/* result = FPMax(lo, hi, FPCR); */
break;
case ReduceOp.ReduceOp_FADD:
/* result = FPAdd(lo, hi, FPCR); */
break;
default:
case ReduceOp.ReduceOp_ADD:
result = lo + hi;
break;
}
return result;
}
public enum ReduceOp {ReduceOp_FMINNUM, ReduceOp_FMAXNUM,
ReduceOp_FMIN, ReduceOp_FMAX,
ReduceOp_FADD, ReduceOp_ADD};
#endregion
}
internal static class Shared