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Fix ~3500 analyser issues

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See merge request ryubing/ryujinx!44
This commit is contained in:
MrKev 2025-05-30 17:08:34 -05:00 • committed by LotP
parent 417df486b1
commit 361d0c5632
622 changed files with 3080 additions and 2652 deletions
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2
src/ARMeilleure/CodeGen/X86/Assembler.cs
View file

@ -1478,7 +1478,7 @@ namespace ARMeilleure.CodeGen.X86
private static bool Is64Bits(OperandType type)
{
return type == OperandType.I64 || type == OperandType.FP64;
return type is OperandType.I64 or OperandType.FP64;
}
private static bool IsImm8(ulong immediate, OperandType type)

1
src/ARMeilleure/CodeGen/X86/AssemblerTable.cs
View file

@ -13,7 +13,6 @@ namespace ARMeilleure.CodeGen.X86
private const int BadOp = 0;
[Flags]
[SuppressMessage("Design", "CA1069: Enums values should not be duplicated")]
private enum InstructionFlags
{
None = 0,

3
src/ARMeilleure/CodeGen/X86/CodeGenContext.cs
View file

@ -1,5 +1,6 @@
using ARMeilleure.CodeGen.RegisterAllocators;
using ARMeilleure.IntermediateRepresentation;
using Microsoft.IO;
using Ryujinx.Common.Memory;
using System.IO;
using System.Numerics;
@ -8,7 +9,7 @@ namespace ARMeilleure.CodeGen.X86
{
class CodeGenContext
{
private readonly Stream _stream;
private readonly RecyclableMemoryStream _stream;
private readonly Operand[] _blockLabels;
public int StreamOffset => (int)_stream.Length;

10
src/ARMeilleure/CodeGen/X86/CodeGenerator.cs
View file

@ -175,8 +175,8 @@ namespace ARMeilleure.CodeGen.X86
// The only blocks which can have 0 successors are exit blocks.
Operation last = block.Operations.Last;
Debug.Assert(last.Instruction == Instruction.Tailcall ||
last.Instruction == Instruction.Return);
Debug.Assert(last.Instruction is Instruction.Tailcall or
Instruction.Return);
}
else
{
@ -478,7 +478,7 @@ namespace ARMeilleure.CodeGen.X86
Debug.Assert(HardwareCapabilities.SupportsVexEncoding);
Debug.Assert(dest.Kind == OperandKind.Register && src1.Kind == OperandKind.Register && src2.Kind == OperandKind.Register);
Debug.Assert(src3.Kind == OperandKind.Register || src3.Kind == OperandKind.Memory);
Debug.Assert(src3.Kind is OperandKind.Register or OperandKind.Memory);
EnsureSameType(dest, src1, src2, src3);
Debug.Assert(dest.Type == OperandType.V128);
@ -788,7 +788,7 @@ namespace ARMeilleure.CodeGen.X86
Operand dest = operation.Destination;
Operand source = operation.GetSource(0);
Debug.Assert(dest.Type == OperandType.FP32 || dest.Type == OperandType.FP64);
Debug.Assert(dest.Type is OperandType.FP32 or OperandType.FP64);
if (dest.Type == OperandType.FP32)
{
@ -1723,7 +1723,7 @@ namespace ARMeilleure.CodeGen.X86
return;
}
Debug.Assert(op1.Kind == OperandKind.Register || op1.Kind == OperandKind.Memory);
Debug.Assert(op1.Kind is OperandKind.Register or OperandKind.Memory);
Debug.Assert(op1.Kind == op2.Kind);
Debug.Assert(op1.Value == op2.Value);
}

19
src/ARMeilleure/CodeGen/X86/PreAllocator.cs
View file

@ -66,6 +66,7 @@ namespace ARMeilleure.CodeGen.X86
{
PreAllocatorSystemV.InsertCallCopies(block.Operations, node);
}
break;
case Instruction.ConvertToFPUI:
@ -81,6 +82,7 @@ namespace ARMeilleure.CodeGen.X86
{
nextNode = PreAllocatorSystemV.InsertLoadArgumentCopy(cctx, ref buffer, block.Operations, preservedArgs, node);
}
break;
case Instruction.Negate:
@ -88,6 +90,7 @@ namespace ARMeilleure.CodeGen.X86
{
GenerateNegate(block.Operations, node);
}
break;
case Instruction.Return:
@ -99,6 +102,7 @@ namespace ARMeilleure.CodeGen.X86
{
PreAllocatorSystemV.InsertReturnCopy(block.Operations, node);
}
break;
case Instruction.Tailcall:
@ -110,6 +114,7 @@ namespace ARMeilleure.CodeGen.X86
{
PreAllocatorSystemV.InsertTailcallCopies(block.Operations, node);
}
break;
case Instruction.VectorInsert8:
@ -117,6 +122,7 @@ namespace ARMeilleure.CodeGen.X86
{
GenerateVectorInsert8(block.Operations, node);
}
break;
case Instruction.Extended:
@ -132,6 +138,7 @@ namespace ARMeilleure.CodeGen.X86
node.SetSources([Const(stackOffset)]);
}
break;
}
}
@ -312,9 +319,9 @@ namespace ARMeilleure.CodeGen.X86
case Instruction.Extended:
{
bool isBlend = node.Intrinsic == Intrinsic.X86Blendvpd ||
node.Intrinsic == Intrinsic.X86Blendvps ||
node.Intrinsic == Intrinsic.X86Pblendvb;
bool isBlend = node.Intrinsic is Intrinsic.X86Blendvpd or
Intrinsic.X86Blendvps or
Intrinsic.X86Pblendvb;
// BLENDVPD, BLENDVPS, PBLENDVB last operand is always implied to be XMM0 when VEX is not supported.
// SHA256RNDS2 always has an implied XMM0 as a last operand.
@ -513,8 +520,8 @@ namespace ARMeilleure.CodeGen.X86
Operand dest = node.Destination;
Operand source = node.GetSource(0);
Debug.Assert(dest.Type == OperandType.FP32 ||
dest.Type == OperandType.FP64, $"Invalid destination type \"{dest.Type}\".");
Debug.Assert(dest.Type is OperandType.FP32 or
OperandType.FP64, $"Invalid destination type \"{dest.Type}\".");
Operation currentNode = node;
@ -761,7 +768,7 @@ namespace ARMeilleure.CodeGen.X86
Comparison compType = (Comparison)comp.AsInt32();
return compType == Comparison.Equal || compType == Comparison.NotEqual;
return compType is Comparison.Equal or Comparison.NotEqual;
}
}

12
src/ARMeilleure/CodeGen/X86/X86Optimizer.cs
View file

@ -248,12 +248,12 @@ namespace ARMeilleure.CodeGen.X86
private static bool IsMemoryLoadOrStore(Instruction inst)
{
return inst == Instruction.Load ||
inst == Instruction.Load16 ||
inst == Instruction.Load8 ||
inst == Instruction.Store ||
inst == Instruction.Store16 ||
inst == Instruction.Store8;
return inst is Instruction.Load or
Instruction.Load16 or
Instruction.Load8 or
Instruction.Store or
Instruction.Store16 or
Instruction.Store8;
}
}
}

1
src/ARMeilleure/CodeGen/X86/X86Register.cs
View file

@ -2,7 +2,6 @@ using System.Diagnostics.CodeAnalysis;
namespace ARMeilleure.CodeGen.X86
{
[SuppressMessage("Design", "CA1069: Enums values should not be duplicated")]
enum X86Register
{
Invalid = -1,