Fix ~3500 analyser issues

See merge request ryubing/ryujinx!44

src/ARMeilleure/Decoders/Decoder.cs

@@ -254,8 +254,8 @@ namespace ARMeilleure.Decoders
             }
 
             // Compare and branch instructions are always conditional.
-            if (opCode.Instruction.Name == InstName.Cbz ||
-                opCode.Instruction.Name == InstName.Cbnz)
+            if (opCode.Instruction.Name is InstName.Cbz or
+                InstName.Cbnz)
             {
                 return false;
             }
@@ -274,9 +274,10 @@ namespace ARMeilleure.Decoders
             {
                 if (opCode is OpCodeT32)
                 {
-                    return opCode.Instruction.Name != InstName.Tst && opCode.Instruction.Name != InstName.Teq &&
-                           opCode.Instruction.Name != InstName.Cmp && opCode.Instruction.Name != InstName.Cmn;
+                    return opCode.Instruction.Name is not InstName.Tst and not InstName.Teq and
+                           not InstName.Cmp and not InstName.Cmn;
                 }
+
                 return true;
             }
 
@@ -284,7 +285,7 @@ namespace ARMeilleure.Decoders
             // register (Rt == 15 or (mask & (1 << 15)) != 0), and cases where there is
             // a write back to PC (wback == true && Rn == 15), however the later may
             // be "undefined" depending on the CPU, so compilers should not produce that.
-            if (opCode is IOpCode32Mem || opCode is IOpCode32MemMult)
+            if (opCode is IOpCode32Mem or IOpCode32MemMult)
             {
                 int rt, rn;
 
@@ -326,15 +327,15 @@ namespace ARMeilleure.Decoders
             }
 
             // Explicit branch instructions.
-            return opCode is IOpCode32BImm ||
-                   opCode is IOpCode32BReg;
+            return opCode is IOpCode32BImm or
+                   IOpCode32BReg;
         }
 
         private static bool IsCall(OpCode opCode)
         {
-            return opCode.Instruction.Name == InstName.Bl ||
-                   opCode.Instruction.Name == InstName.Blr ||
-                   opCode.Instruction.Name == InstName.Blx;
+            return opCode.Instruction.Name is InstName.Bl or
+                   InstName.Blr or
+                   InstName.Blx;
         }
 
         private static bool IsException(OpCode opCode)
@@ -344,9 +345,9 @@ namespace ARMeilleure.Decoders
 
         private static bool IsTrap(OpCode opCode)
         {
-            return opCode.Instruction.Name == InstName.Brk ||
-                   opCode.Instruction.Name == InstName.Trap ||
-                   opCode.Instruction.Name == InstName.Und;
+            return opCode.Instruction.Name is InstName.Brk or
+                   InstName.Trap or
+                   InstName.Und;
         }
 
         public static OpCode DecodeOpCode(IMemoryManager memory, ulong address, ExecutionMode mode)

src/ARMeilleure/Decoders/DecoderHelper.cs

@@ -162,6 +162,7 @@ namespace ARMeilleure.Decoders
                     }
                 }
             }
+
             return false;
         }
     }

src/ARMeilleure/Decoders/OpCode32SimdDupGP.cs

@@ -20,6 +20,7 @@ namespace ARMeilleure.Decoders
                 Instruction = InstDescriptor.Undefined;
                 return;
             }
+
             Q = ((opCode >> 21) & 0x1) != 0;
 
             RegisterSize = Q ? RegisterSize.Simd128 : RegisterSize.Simd64;

src/ARMeilleure/Decoders/OpCode32SimdMemPair.cs

@@ -40,7 +40,7 @@ namespace ARMeilleure.Decoders
             Rn = (opCode >> 16) & 0xf;
 
             WBack = Rm != RegisterAlias.Aarch32Pc;
-            RegisterIndex = Rm != RegisterAlias.Aarch32Pc && Rm != RegisterAlias.Aarch32Sp;
+            RegisterIndex = Rm is not RegisterAlias.Aarch32Pc and not RegisterAlias.Aarch32Sp;
 
             Regs = _regsMap[(opCode >> 8) & 0xf];
 

src/ARMeilleure/Decoders/OpCode32SimdMemSingle.cs

@@ -45,7 +45,7 @@ namespace ARMeilleure.Decoders
             Rn = (opCode >> 16) & 0xf;
 
             WBack = Rm != RegisterAlias.Aarch32Pc;
-            RegisterIndex = Rm != RegisterAlias.Aarch32Pc && Rm != RegisterAlias.Aarch32Sp;
+            RegisterIndex = Rm is not RegisterAlias.Aarch32Pc and not RegisterAlias.Aarch32Sp;
         }
     }
 }

src/ARMeilleure/Decoders/OpCodeMemImm.cs

@@ -28,8 +28,8 @@ namespace ARMeilleure.Decoders
             MemOp type = WBack ? (MemOp)((opCode >> 10) & 3) : MemOp.Unsigned;
 
             PostIdx = type == MemOp.PostIndexed;
-            Unscaled = type == MemOp.Unscaled ||
-                       type == MemOp.Unprivileged;
+            Unscaled = type is MemOp.Unscaled or
+                       MemOp.Unprivileged;
 
             // Unscaled and Unprivileged doesn't write back,
             // but they do use the 9-bits Signed Immediate.

src/ARMeilleure/Decoders/OpCodeTable.cs

@@ -1381,6 +1381,7 @@ namespace ARMeilleure.Decoders
             {
                 thumbEncoding = $"1110{thumbEncoding.AsSpan(4)}";
             }
+
             SetT32(thumbEncoding, name, emitter, makeOpT32);
         }
 
@@ -1409,6 +1410,7 @@ namespace ARMeilleure.Decoders
             {
                 throw new ArgumentException("Invalid ASIMD instruction encoding");
             }
+
             SetT32(thumbEncoding, name, emitter, makeOpT32);
         }