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Fix ~3500 analyser issues

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See merge request ryubing/ryujinx!44
This commit is contained in:
MrKev 2025-05-30 17:08:34 -05:00 • committed by LotP
parent 417df486b1
commit 361d0c5632
622 changed files with 3080 additions and 2652 deletions
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2
src/ARMeilleure/Instructions/InstEmitAlu32.cs
View file

@ -899,6 +899,7 @@ namespace ARMeilleure.Instructions
{
n = context.ShiftLeft(n, Const(shift));
}
break;
case ShiftType.Asr:
if (shift == 32)
@ -909,6 +910,7 @@ namespace ARMeilleure.Instructions
{
n = context.ShiftRightSI(n, Const(shift));
}
break;
}

3
src/ARMeilleure/Instructions/InstEmitAluHelper.cs
View file

@ -266,7 +266,7 @@ namespace ARMeilleure.Instructions
}
}
private static Exception InvalidOpCodeType(OpCode opCode)
private static InvalidOperationException InvalidOpCodeType(OpCode opCode)
{
return new InvalidOperationException($"Invalid OpCode type \"{opCode?.GetType().Name ?? "null"}\".");
}
@ -318,6 +318,7 @@ namespace ARMeilleure.Instructions
{
m = GetRrxC(context, m, setCarry);
}
break;
}
}

2
src/ARMeilleure/Instructions/InstEmitHashHelper.cs
View file

@ -17,7 +17,7 @@ namespace ARMeilleure.Instructions
public static Operand EmitCrc32(ArmEmitterContext context, Operand crc, Operand value, int size, bool castagnoli)
{
Debug.Assert(crc.Type.IsInteger() && value.Type.IsInteger());
Debug.Assert(size >= 0 && size < 4);
Debug.Assert(size is >= 0 and < 4);
Debug.Assert((size < 3) || (value.Type == OperandType.I64));
if (castagnoli && Optimizations.UseSse42)

1
src/ARMeilleure/Instructions/InstEmitHelper.cs
View file

@ -90,6 +90,7 @@ namespace ARMeilleure.Instructions
{
value = context.ConvertI64ToI32(value);
}
Operand reg = Register(GetRegisterAlias(context.Mode, regIndex), RegisterType.Integer, OperandType.I32);
context.Copy(reg, value);

2
src/ARMeilleure/Instructions/InstEmitMemoryEx.cs
View file

@ -140,7 +140,7 @@ namespace ARMeilleure.Instructions
if (pair)
{
Debug.Assert(op.Size == 2 || op.Size == 3, "Invalid size for pairwise store.");
Debug.Assert(op.Size is 2 or 3, "Invalid size for pairwise store.");
Operand t2 = GetIntOrZR(context, op.Rt2);

1
src/ARMeilleure/Instructions/InstEmitMemoryExHelper.cs
View file

@ -42,6 +42,7 @@ namespace ARMeilleure.Instructions
{
context.Store(exValuePtr, Const(0UL));
}
if (size < 4)
{
context.Store(context.Add(exValuePtr, Const(exValuePtr.Type, 8L)), Const(0UL));

11
src/ARMeilleure/Instructions/InstEmitMemoryHelper.cs
View file

@ -59,7 +59,7 @@ namespace ARMeilleure.Instructions
{
Operand value = GetInt(context, rt);
if (ext == Extension.Sx32 || ext == Extension.Sx64)
if (ext is Extension.Sx32 or Extension.Sx64)
{
OperandType destType = ext == Extension.Sx64 ? OperandType.I64 : OperandType.I32;
@ -123,9 +123,9 @@ namespace ARMeilleure.Instructions
private static bool IsSimd(ArmEmitterContext context)
{
return context.CurrOp is IOpCodeSimd &&
!(context.CurrOp is OpCodeSimdMemMs ||
context.CurrOp is OpCodeSimdMemSs);
return context.CurrOp is IOpCodeSimd and
not (OpCodeSimdMemMs or
OpCodeSimdMemSs);
}
public static Operand EmitReadInt(ArmEmitterContext context, Operand address, int size)
@ -717,7 +717,7 @@ namespace ARMeilleure.Instructions
};
}
private static Exception InvalidOpCodeType(OpCode opCode)
private static InvalidOperationException InvalidOpCodeType(OpCode opCode)
{
return new InvalidOperationException($"Invalid OpCode type \"{opCode?.GetType().Name ?? "null"}\".");
}
@ -768,6 +768,7 @@ namespace ARMeilleure.Instructions
{
m = InstEmitAluHelper.GetRrxC(context, m, setCarry);
}
break;
}
}

1
src/ARMeilleure/Instructions/InstEmitMul.cs
View file

@ -33,7 +33,6 @@ namespace ARMeilleure.Instructions
public static void Umsubl(ArmEmitterContext context) => EmitMull(context, MullFlags.Subtract);
[Flags]
[SuppressMessage("Design", "CA1069: Enums values should not be duplicated")]
private enum MullFlags
{
Subtract = 0,

2
src/ARMeilleure/Instructions/InstEmitSimdArithmetic.cs
View file

@ -5266,7 +5266,7 @@ namespace ARMeilleure.Instructions
private static Operand EmitSse2Sll_128(ArmEmitterContext context, Operand op, int shift)
{
// The upper part of op is assumed to be zero.
Debug.Assert(shift >= 0 && shift < 64);
Debug.Assert(shift is >= 0 and < 64);
if (shift == 0)
{

8
src/ARMeilleure/Instructions/InstEmitSimdArithmetic32.cs
View file

@ -231,10 +231,12 @@ namespace ARMeilleure.Instructions
{
result |= (long)((i >= end || i < start) ? 0x80 : b++) << (i * 8);
}
for (int i = 8; i < 16; i++)
{
result2 |= (long)((i >= end || i < start) ? 0x80 : b++) << ((i - 8) * 8);
}
return (result2, result);
}
@ -261,6 +263,7 @@ namespace ARMeilleure.Instructions
nMaskHigh = nMaskLow + 0x0808080808080808L;
mMaskHigh = mMaskLow + 0x0808080808080808L;
}
nMask = X86GetElements(context, nMaskHigh, nMaskLow);
mMask = X86GetElements(context, mMaskHigh, mMaskLow);
Operand nPart = context.AddIntrinsic(Intrinsic.X86Pshufb, n, nMask);
@ -285,6 +288,7 @@ namespace ARMeilleure.Instructions
{
extract = EmitVectorExtractZx32(context, op.Qn, op.In + byteOff, op.Size);
}
byteOff++;
res = EmitVectorInsert(context, res, extract, op.Id + index, op.Size);
@ -1304,6 +1308,7 @@ namespace ARMeilleure.Instructions
case 2:
return context.AddIntrinsic(Intrinsic.X86Shufps, op1, op1, Const(1 | (0 << 2) | (3 << 4) | (2 << 6)));
}
break;
case 2:
// Rev32
@ -1316,6 +1321,7 @@ namespace ARMeilleure.Instructions
mask = X86GetElements(context, 0x0d0c0f0e_09080b0aL, 0x05040706_01000302L);
return context.AddIntrinsic(Intrinsic.X86Pshufb, op1, mask);
}
break;
case 1:
// Rev16
@ -1341,6 +1347,7 @@ namespace ARMeilleure.Instructions
case 3:
return context.ByteSwap(op1);
}
break;
case 1:
switch (op.Size)
@ -1355,6 +1362,7 @@ namespace ARMeilleure.Instructions
context.BitwiseOr(context.ShiftRightUI(context.BitwiseAnd(op1, Const(0x0000ffff00000000ul)), Const(16)),
context.ShiftLeft(context.BitwiseAnd(op1, Const(0x00000000ffff0000ul)), Const(16))));
}
break;
case 2:
// Swap upper and lower halves.

10
src/ARMeilleure/Instructions/InstEmitSimdCvt.cs
View file

@ -1119,7 +1119,7 @@ namespace ARMeilleure.Instructions
private static Operand EmitFPConvert(ArmEmitterContext context, Operand value, int size, bool signed)
{
Debug.Assert(value.Type == OperandType.I32 || value.Type == OperandType.I64);
Debug.Assert(value.Type is OperandType.I32 or OperandType.I64);
Debug.Assert((uint)size < 2);
OperandType type = size == 0 ? OperandType.FP32 : OperandType.FP64;
@ -1136,7 +1136,7 @@ namespace ARMeilleure.Instructions
private static Operand EmitScalarFcvts(ArmEmitterContext context, Operand value, int fBits)
{
Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
Debug.Assert(value.Type is OperandType.FP32 or OperandType.FP64);
value = EmitF2iFBitsMul(context, value, fBits);
@ -1160,7 +1160,7 @@ namespace ARMeilleure.Instructions
private static Operand EmitScalarFcvtu(ArmEmitterContext context, Operand value, int fBits)
{
Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
Debug.Assert(value.Type is OperandType.FP32 or OperandType.FP64);
value = EmitF2iFBitsMul(context, value, fBits);
@ -1184,7 +1184,7 @@ namespace ARMeilleure.Instructions
private static Operand EmitF2iFBitsMul(ArmEmitterContext context, Operand value, int fBits)
{
Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
Debug.Assert(value.Type is OperandType.FP32 or OperandType.FP64);
if (fBits == 0)
{
@ -1203,7 +1203,7 @@ namespace ARMeilleure.Instructions
private static Operand EmitI2fFBitsMul(ArmEmitterContext context, Operand value, int fBits)
{
Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.FP64);
Debug.Assert(value.Type is OperandType.FP32 or OperandType.FP64);
if (fBits == 0)
{

4
src/ARMeilleure/Instructions/InstEmitSimdCvt32.cs
View file

@ -385,6 +385,7 @@ namespace ARMeilleure.Instructions
{
res = context.AddIntrinsic(Intrinsic.X86Cvtsd2ss, context.VectorZero(), res);
}
res = context.AddIntrinsic(Intrinsic.X86Vcvtps2ph, res, Const(X86GetRoundControl(FPRoundingMode.ToNearest)));
res = context.VectorExtract16(res, 0);
InsertScalar16(context, op.Vd, op.T, res);
@ -397,6 +398,7 @@ namespace ARMeilleure.Instructions
{
res = context.AddIntrinsic(Intrinsic.X86Cvtss2sd, context.VectorZero(), res);
}
res = context.VectorExtract(op.Size == 1 ? OperandType.I64 : OperandType.I32, res, 0);
InsertScalar(context, op.Vd, res);
}
@ -635,7 +637,7 @@ namespace ARMeilleure.Instructions
private static Operand EmitFPConvert(ArmEmitterContext context, Operand value, OperandType type, bool signed)
{
Debug.Assert(value.Type == OperandType.I32 || value.Type == OperandType.I64);
Debug.Assert(value.Type is OperandType.I32 or OperandType.I64);
if (signed)
{

12
src/ARMeilleure/Instructions/InstEmitSimdHelper.cs
View file

@ -363,7 +363,7 @@ namespace ARMeilleure.Instructions
public static Operand EmitCountSetBits8(ArmEmitterContext context, Operand op) // "size" is 8 (SIMD&FP Inst.).
{
Debug.Assert(op.Type == OperandType.I32 || op.Type == OperandType.I64);
Debug.Assert(op.Type is OperandType.I32 or OperandType.I64);
Operand op0 = context.Subtract(op, context.BitwiseAnd(context.ShiftRightUI(op, Const(1)), Const(op.Type, 0x55L)));
@ -489,7 +489,7 @@ namespace ARMeilleure.Instructions
public static Operand EmitRoundByRMode(ArmEmitterContext context, Operand op)
{
Debug.Assert(op.Type == OperandType.FP32 || op.Type == OperandType.FP64);
Debug.Assert(op.Type is OperandType.FP32 or OperandType.FP64);
Operand lbl1 = Label();
Operand lbl2 = Label();
@ -1676,7 +1676,7 @@ namespace ARMeilleure.Instructions
int eSize = 8 << size;
Debug.Assert(op.Type == OperandType.I64);
Debug.Assert(eSize == 8 || eSize == 16 || eSize == 32 || eSize == 64);
Debug.Assert(eSize is 8 or 16 or 32 or 64);
Operand lbl1 = Label();
Operand lblEnd = Label();
@ -1709,7 +1709,7 @@ namespace ARMeilleure.Instructions
int eSize = 8 << size;
Debug.Assert(op.Type == OperandType.I64);
Debug.Assert(eSize == 8 || eSize == 16 || eSize == 32 || eSize == 64);
Debug.Assert(eSize is 8 or 16 or 32 or 64);
Operand lblEnd = Label();
@ -1735,7 +1735,7 @@ namespace ARMeilleure.Instructions
int eSizeDst = 8 << sizeDst;
Debug.Assert(op.Type == OperandType.I64);
Debug.Assert(eSizeDst == 8 || eSizeDst == 16 || eSizeDst == 32);
Debug.Assert(eSizeDst is 8 or 16 or 32);
Operand lbl1 = Label();
Operand lblEnd = Label();
@ -1768,7 +1768,7 @@ namespace ARMeilleure.Instructions
int eSizeDst = 8 << sizeDst;
Debug.Assert(op.Type == OperandType.I64);
Debug.Assert(eSizeDst == 8 || eSizeDst == 16 || eSizeDst == 32);
Debug.Assert(eSizeDst is 8 or 16 or 32);
Operand lblEnd = Label();

7
src/ARMeilleure/Instructions/InstEmitSimdHelper32.cs
View file

@ -31,7 +31,7 @@ namespace ARMeilleure.Instructions
{
Debug.Assert(type != OperandType.V128);
if (type == OperandType.FP64 || type == OperandType.I64)
if (type is OperandType.FP64 or OperandType.I64)
{
// From dreg.
return context.VectorExtract(type, GetVecA32(reg >> 1), reg & 1);
@ -48,7 +48,7 @@ namespace ARMeilleure.Instructions
Debug.Assert(value.Type != OperandType.V128);
Operand vec, insert;
if (value.Type == OperandType.FP64 || value.Type == OperandType.I64)
if (value.Type is OperandType.FP64 or OperandType.I64)
{
// From dreg.
vec = GetVecA32(reg >> 1);
@ -71,7 +71,7 @@ namespace ARMeilleure.Instructions
public static void InsertScalar16(ArmEmitterContext context, int reg, bool top, Operand value)
{
Debug.Assert(value.Type == OperandType.FP32 || value.Type == OperandType.I32);
Debug.Assert(value.Type is OperandType.FP32 or OperandType.I32);
Operand vec, insert;
vec = GetVecA32(reg >> 2);
@ -880,6 +880,7 @@ namespace ARMeilleure.Instructions
{
res = EmitMoveDoubleWordToSide(context, res, side, op.Vd);
}
res = EmitDoubleWordInsert(context, d, res, op.Vd);
}

1
src/ARMeilleure/Instructions/InstEmitSimdHelper32Arm64.cs
View file

@ -146,6 +146,7 @@ namespace ARMeilleure.Instructions
{
res = EmitMoveDoubleWordToSide(context, res, side, op.Vd);
}
res = EmitDoubleWordInsert(context, d, res, op.Vd);
}

1
src/ARMeilleure/Instructions/InstEmitSimdLogical32.cs
View file

@ -268,6 +268,7 @@ namespace ARMeilleure.Instructions
{
m = context.BitwiseNot(m);
}
return context.BitwiseExclusiveOr(
context.BitwiseAnd(m,
context.BitwiseExclusiveOr(d, n)), d);

1
src/ARMeilleure/Instructions/InstEmitSimdMemory32.cs
View file

@ -110,6 +110,7 @@ namespace ARMeilleure.Instructions
EmitStoreSimd(context, address, d >> 1, index, op.Size);
}
}
offset += eBytes;
d += op.Increment;
}

11
src/ARMeilleure/Instructions/InstEmitSimdShift.cs
View file

@ -1634,7 +1634,7 @@ namespace ARMeilleure.Instructions
int eSize = 8 << size;
Debug.Assert(op.Type == OperandType.I64);
Debug.Assert(eSize == 8 || eSize == 16 || eSize == 32 || eSize == 64);
Debug.Assert(eSize is 8 or 16 or 32 or 64);
Operand res = context.AllocateLocal(OperandType.I64);
@ -1657,7 +1657,7 @@ namespace ARMeilleure.Instructions
int eSize = 8 << size;
Debug.Assert(op.Type == OperandType.I64);
Debug.Assert(eSize == 8 || eSize == 16 || eSize == 32 || eSize == 64);
Debug.Assert(eSize is 8 or 16 or 32 or 64);
Operand lblEnd = Label();
@ -1732,7 +1732,7 @@ namespace ARMeilleure.Instructions
Debug.Assert(op.Type == OperandType.I64);
Debug.Assert(shiftLsB.Type == OperandType.I32);
Debug.Assert(eSize == 8 || eSize == 16 || eSize == 32 || eSize == 64);
Debug.Assert(eSize is 8 or 16 or 32 or 64);
Operand lbl1 = Label();
Operand lblEnd = Label();
@ -1769,7 +1769,7 @@ namespace ARMeilleure.Instructions
Debug.Assert(op.Type == OperandType.I64);
Debug.Assert(shiftLsB.Type == OperandType.I32);
Debug.Assert(eSize == 8 || eSize == 16 || eSize == 32 || eSize == 64);
Debug.Assert(eSize is 8 or 16 or 32 or 64);
Operand lbl1 = Label();
Operand lbl2 = Label();
@ -1813,6 +1813,7 @@ namespace ARMeilleure.Instructions
? EmitSignedSrcSatQ(context, shl, size, signedDst: true)
: EmitUnsignedSrcSatQ(context, shl, size, signedDst: false));
}
context.Branch(lblEnd);
context.MarkLabel(lblEnd);
@ -1850,6 +1851,7 @@ namespace ARMeilleure.Instructions
{
context.Copy(res, sar);
}
context.Branch(lblEnd);
context.MarkLabel(lblEnd);
@ -1906,6 +1908,7 @@ namespace ARMeilleure.Instructions
Operand right = context.BitwiseOr(shr, context.ShiftRightUI(oneShl63UL, context.Subtract(shift, one)));
context.Copy(res, context.ConditionalSelect(isEqual, oneUL, right));
}
context.Branch(lblEnd);
context.MarkLabel(lblEnd);

4
src/ARMeilleure/Instructions/NativeInterface.cs
View file

@ -69,13 +69,13 @@ namespace ARMeilleure.Instructions
[UnmanagedCallersOnly]
public static ulong GetCtrEl0()
{
return GetContext().CtrEl0;
return ExecutionContext.CtrEl0;
}
[UnmanagedCallersOnly]
public static ulong GetDczidEl0()
{
return GetContext().DczidEl0;
return ExecutionContext.DczidEl0;
}
[UnmanagedCallersOnly]

34
src/ARMeilleure/Instructions/SoftFloat.cs
View file

@ -24,7 +24,7 @@ namespace ARMeilleure.Instructions
{
uint src = (uint)idx + 256u;
Debug.Assert(256u <= src && src < 512u);
Debug.Assert(src is >= 256u and < 512u);
src = (src << 1) + 1u;
@ -32,7 +32,7 @@ namespace ARMeilleure.Instructions
uint dst = (aux + 1u) >> 1;
Debug.Assert(256u <= dst && dst < 512u);
Debug.Assert(dst is >= 256u and < 512u);
tbl[idx] = (byte)(dst - 256u);
}
@ -48,7 +48,7 @@ namespace ARMeilleure.Instructions
{
uint src = (uint)idx + 128u;
Debug.Assert(128u <= src && src < 512u);
Debug.Assert(src is >= 128u and < 512u);
if (src < 256u)
{
@ -69,7 +69,7 @@ namespace ARMeilleure.Instructions
uint dst = (aux + 1u) >> 1;
Debug.Assert(256u <= dst && dst < 512u);
Debug.Assert(dst is >= 256u and < 512u);
tbl[idx] = (byte)(dst - 256u);
}
@ -322,7 +322,7 @@ namespace ARMeilleure.Instructions
float result;
if (type == FPType.SNaN || type == FPType.QNaN)
if (type is FPType.SNaN or FPType.QNaN)
{
if ((context.Fpcr & FPCR.Dn) != 0)
{
@ -498,7 +498,7 @@ namespace ARMeilleure.Instructions
double result;
if (type == FPType.SNaN || type == FPType.QNaN)
if (type is FPType.SNaN or FPType.QNaN)
{
if ((context.Fpcr & FPCR.Dn) != 0)
{
@ -676,7 +676,7 @@ namespace ARMeilleure.Instructions
ushort resultBits;
if (type == FPType.SNaN || type == FPType.QNaN)
if (type is FPType.SNaN or FPType.QNaN)
{
if (altHp)
{
@ -1086,7 +1086,7 @@ namespace ARMeilleure.Instructions
{
return FPMaxFpscrImpl(value1, value2, standardFpscr == 1);
}
private static float FPMaxFpscrImpl(float value1, float value2, bool standardFpscr)
{
ExecutionContext context = NativeInterface.GetContext();
@ -1522,7 +1522,7 @@ namespace ARMeilleure.Instructions
float result;
if (type == FPType.SNaN || type == FPType.QNaN)
if (type is FPType.SNaN or FPType.QNaN)
{
result = FPProcessNaN(type, op, context, fpcr);
}
@ -1689,7 +1689,7 @@ namespace ARMeilleure.Instructions
float result;
if (type == FPType.SNaN || type == FPType.QNaN)
if (type is FPType.SNaN or FPType.QNaN)
{
result = FPProcessNaN(type, op, context, fpcr);
}
@ -1726,7 +1726,7 @@ namespace ARMeilleure.Instructions
float result;
if (type == FPType.SNaN || type == FPType.QNaN)
if (type is FPType.SNaN or FPType.QNaN)
{
result = FPProcessNaN(type, op, context, fpcr);
}
@ -1920,7 +1920,7 @@ namespace ARMeilleure.Instructions
float result;
if (type == FPType.SNaN || type == FPType.QNaN)
if (type is FPType.SNaN or FPType.QNaN)
{
result = FPProcessNaN(type, op, context, fpcr);
}
@ -2211,7 +2211,7 @@ namespace ARMeilleure.Instructions
ushort resultBits;
if (type == FPType.SNaN || type == FPType.QNaN)
if (type is FPType.SNaN or FPType.QNaN)
{
if (altHp)
{
@ -3057,7 +3057,7 @@ namespace ARMeilleure.Instructions
double result;
if (type == FPType.SNaN || type == FPType.QNaN)
if (type is FPType.SNaN or FPType.QNaN)
{
result = FPProcessNaN(type, op, context, fpcr);
}
@ -3224,7 +3224,7 @@ namespace ARMeilleure.Instructions
double result;
if (type == FPType.SNaN || type == FPType.QNaN)
if (type is FPType.SNaN or FPType.QNaN)
{
result = FPProcessNaN(type, op, context, fpcr);
}
@ -3261,7 +3261,7 @@ namespace ARMeilleure.Instructions
double result;
if (type == FPType.SNaN || type == FPType.QNaN)
if (type is FPType.SNaN or FPType.QNaN)
{
result = FPProcessNaN(type, op, context, fpcr);
}
@ -3455,7 +3455,7 @@ namespace ARMeilleure.Instructions
double result;
if (type == FPType.SNaN || type == FPType.QNaN)
if (type is FPType.SNaN or FPType.QNaN)
{
result = FPProcessNaN(type, op, context, fpcr);
}