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Fix ~3500 analyser issues

Browse source 
See merge request ryubing/ryujinx!44
This commit is contained in:
MrKev 2025-05-30 17:08:34 -05:00 • committed by LotP
parent 417df486b1
commit 361d0c5632
622 changed files with 3080 additions and 2652 deletions
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4
src/Ryujinx.Cpu/AddressTable.cs
View file

@ -51,7 +51,7 @@ namespace ARMeilleure.Common
{
SparseMemoryBlock block = new(size, pageInit, null);
_trackingEvent = (ulong address, ulong size, bool write) =>
_trackingEvent = (address, size, write) =>
{
ulong pointer = (ulong)block.Block.Pointer + address;
ensureMapped((IntPtr)pointer);
@ -181,7 +181,7 @@ namespace ARMeilleure.Common
public static AddressTable<TEntry> CreateForArm(bool for64Bits, MemoryManagerType type)
{
// Assume software memory means that we don't want to use any signal handlers.
bool sparse = type != MemoryManagerType.SoftwareMmu && type != MemoryManagerType.SoftwarePageTable;
bool sparse = type is not MemoryManagerType.SoftwareMmu and not MemoryManagerType.SoftwarePageTable;
return new AddressTable<TEntry>(AddressTablePresets.GetArmPreset(for64Bits, sparse), sparse);
}

2
src/Ryujinx.Cpu/AppleHv/HvAddressSpaceRange.cs
View file

@ -359,7 +359,7 @@ namespace Ryujinx.Cpu.AppleHv
private static void ValidateEntriesCount(int count)
{
Debug.Assert(count >= 0 && count <= LevelCount, $"Entries count {count} is invalid.");
Debug.Assert(count is >= 0 and <= LevelCount, $"Entries count {count} is invalid.");
}
public void Dispose()

2
src/Ryujinx.Cpu/AppleHv/HvExecutionContext.cs
View file

@ -159,7 +159,7 @@ namespace Ryujinx.Cpu.AppleHv
address = SynchronousException(memoryManager, ref vcpu);
HvApi.hv_vcpu_set_reg(vcpu.Handle, HvReg.PC, address).ThrowOnError();
}
else if (reason == HvExitReason.Canceled || reason == HvExitReason.VTimerActivated)
else if (reason is HvExitReason.Canceled or HvExitReason.VTimerActivated)
{
if (GetAndClearInterruptRequested())
{

4
src/Ryujinx.Cpu/ITickSource.cs
View file

@ -9,12 +9,12 @@ namespace Ryujinx.Cpu
public interface ITickSource : ICounter
{
public const long RealityTickScalar = 100;
/// <summary>
/// Time elapsed since the counter was created.
/// </summary>
TimeSpan ElapsedTime { get; }
/// <summary>
/// Clock tick scalar, in percent points (100 = 1.0).
/// </summary>

1
src/Ryujinx.Cpu/Jit/HostTracked/AddressIntrusiveRedBlackTree.cs
View file

@ -29,6 +29,7 @@ namespace Ryujinx.Cpu.Jit.HostTracked
return node;
}
}
return null;
}
}

4
src/Ryujinx.Cpu/Jit/HostTracked/AddressSpacePartitionAllocator.cs
View file

@ -115,7 +115,7 @@ namespace Ryujinx.Cpu.Jit.HostTracked
}
private readonly AddressIntrusiveRedBlackTree<Mapping> _mappingTree;
// type is not Lock due to the unique usage of this mechanism,
// an arbitrary object is used as the lock passed in by constructor.
private readonly object _lock;
@ -177,7 +177,7 @@ namespace Ryujinx.Cpu.Jit.HostTracked
private readonly MemoryTracking _tracking;
private readonly Func<ulong, ulong> _readPtCallback;
// type is not Lock due to the unique usage of this mechanism,
// an arbitrary object is used as the lock passed in by constructor.
private readonly object _lock;

2
src/Ryujinx.Cpu/LightningJit/Arm32/InstName.cs
View file

@ -531,7 +531,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32
{
public static bool IsCall(this InstName name)
{
return name == InstName.BlI || name == InstName.BlxR;
return name is InstName.BlI or InstName.BlxR;
}
public static bool IsSystem(this InstName name)

2
src/Ryujinx.Cpu/LightningJit/Arm32/InstTableT32.cs
View file

@ -526,7 +526,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32
new(0x00000041, 0x00000041)
];
List<InstInfoForTable> insts =
List<InstInfoForTable> insts =
[
new(0xF1400000, 0xFBE08000, InstName.AdcI, T.AdcIT1, IsaVersion.v80, InstFlags.Rd),
new(0xEB400000, 0xFFE08000, InstName.AdcR, T.AdcRT2, IsaVersion.v80, InstFlags.Rd),

5
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/Compiler.cs
View file

@ -493,7 +493,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
{
delta = targetIndex - branchIndex;
if (delta >= -Encodable26BitsOffsetLimit && delta < Encodable26BitsOffsetLimit)
if (delta is >= (-Encodable26BitsOffsetLimit) and < Encodable26BitsOffsetLimit)
{
writer.WriteInstructionAt(branchIndex, encoding | (uint)(delta & 0x3ffffff));
@ -559,7 +559,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
}
}
Debug.Assert(name == InstName.B || name == InstName.Cbnz, $"Unknown branch instruction \"{name}\".");
Debug.Assert(name is InstName.B or InstName.Cbnz, $"Unknown branch instruction \"{name}\".");
}
private static void RewriteCallInstructionWithTarget(in Context context, uint targetAddress, uint nextAddress, int branchIndex)
@ -745,6 +745,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
InstEmitSystem.WriteUdf(context.Writer, context.RegisterAllocator, context.TailMerger, context.GetReservedStackOffset(), pc, imm);
break;
}
context.LoadFromContext();
break;
case BranchType.ReadCntpct:

1
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitAlu.cs
View file

@ -736,6 +736,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
{
m = GetRrxC(context, dest, m, carryOut);
}
break;
}
}

2
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitFlow.cs
View file

@ -142,7 +142,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
int tempRegister;
int tempGuestAddress = -1;
bool inlineLookup = guestAddress.Kind != OperandKind.Constant &&
bool inlineLookup = guestAddress.Kind != OperandKind.Constant &&
funcTable is { Sparse: true };
if (guestAddress.Kind == OperandKind.Constant)

30
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitNeonCommon.cs
View file

@ -118,7 +118,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
public static void EmitScalarUnaryF(CodeGenContext context, uint rd, uint rm, uint size, Action<Operand, Operand, uint> action)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@ -133,7 +133,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
public static void EmitScalarUnaryF(CodeGenContext context, uint rd, uint rm, uint size, Action<Operand, Operand, uint> action, Action<Operand, Operand> actionHalf)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@ -161,7 +161,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
uint sf,
Action<Operand, Operand, uint, uint> action)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@ -182,7 +182,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
uint sf,
Action<Operand, Operand, uint, uint> action)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@ -197,7 +197,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
public static void EmitScalarUnaryFixedF(CodeGenContext context, uint rd, uint rm, uint fbits, uint size, bool is16Bit, Action<Operand, Operand, uint, uint> action)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@ -214,7 +214,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
public static void EmitScalarBinaryF(CodeGenContext context, uint rd, uint rn, uint rm, uint size, Action<Operand, Operand, Operand, uint> action)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@ -252,7 +252,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
public static void EmitScalarTernaryRdF(CodeGenContext context, uint rd, uint rn, uint rm, uint size, Action<Operand, Operand, Operand, uint> action)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@ -276,7 +276,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
uint size,
Action<Operand, Operand, Operand, Operand, uint> action)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@ -300,7 +300,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
bool negD,
bool negProduct)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
@ -918,7 +918,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
Action<Operand, Operand, uint, uint> action,
Action<Operand, Operand, uint> actionHalf)
{
Debug.Assert(sz == 0 || sz == 1);
Debug.Assert(sz is 0 or 1);
if (q == 0)
{
@ -962,7 +962,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
Action<Operand, Operand, uint, uint> action,
Action<Operand, Operand, uint> actionHalf)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
Debug.Assert(size != 3 || q == 1);
if (q == 0)
@ -1007,7 +1007,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
uint q,
Action<Operand, Operand, uint, uint, uint> action)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
Debug.Assert(size != 3 || q == 1);
(uint immb, uint immh) = GetImmbImmh(fbits, size);
@ -1040,7 +1040,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
Action<Operand, Operand, Operand, uint, uint> action,
Action<Operand, Operand, Operand, uint> actionHalf)
{
Debug.Assert(sz == 0 || sz == 1);
Debug.Assert(sz is 0 or 1);
if (q == 0)
{
@ -1100,7 +1100,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
Action<Operand, Operand, Operand, uint, uint> action,
Action<Operand, Operand, Operand, uint> actionHalf)
{
Debug.Assert(sz == 0 || sz == 1);
Debug.Assert(sz is 0 or 1);
if (q == 0)
{
@ -1148,7 +1148,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
uint q,
bool negProduct)
{
Debug.Assert(sz == 0 || sz == 1);
Debug.Assert(sz is 0 or 1);
if (q == 0)
{

2
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitNeonMemory.cs
View file

@ -467,7 +467,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
private static void EmitMemory1234InstructionCore(CodeGenContext context, uint rn, uint rm, int bytes, Action<Operand> callback)
{
bool wBack = rm != RegisterUtils.PcRegister;
bool registerIndex = rm != RegisterUtils.PcRegister && rm != RegisterUtils.SpRegister;
bool registerIndex = rm is not RegisterUtils.PcRegister and not RegisterUtils.SpRegister;
Operand rnOperand = InstEmitCommon.GetInputGpr(context, rn);

4
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitNeonMove.cs
View file

@ -252,7 +252,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
}
else
{
Debug.Assert(opc1 == 0 || opc1 == 1);
Debug.Assert(opc1 is 0 or 1);
Debug.Assert(opc2 == 0);
index = opc1 & 1u;
@ -307,7 +307,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
}
else
{
Debug.Assert(opc1 == 0 || opc1 == 1);
Debug.Assert(opc1 is 0 or 1);
Debug.Assert(opc2 == 0);
Debug.Assert(!u);

3
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitSystem.cs
View file

@ -60,6 +60,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
return;
}
}
break;
}
}
@ -109,6 +110,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
break;
}
}
break;
}
@ -142,6 +144,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
context.Arm64Assembler.B(0);
return;
}
break;
}

2
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitVfpCompare.cs
View file

@ -27,7 +27,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
private static void EmitVcmpVcmpe(CodeGenContext context, uint cond, uint rd, uint rm, uint size, bool zero, bool e)
{
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;
uint ftype = size ^ 2u;

2
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitVfpConvert.cs
View file

@ -231,7 +231,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
{
bool unsigned = (op & 1) == 0;
Debug.Assert(size == 1 || size == 2 || size == 3);
Debug.Assert(size is 1 or 2 or 3);
bool singleRegs = size != 3;

2
src/Ryujinx.Cpu/LightningJit/Arm64/InstName.cs
View file

@ -1044,7 +1044,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64
{
public static bool IsCall(this InstName name)
{
return name == InstName.Bl || name == InstName.Blr;
return name is InstName.Bl or InstName.Blr;
}
public static bool IsControlFlowOrException(this InstName name)

9
src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/Compiler.cs
View file

@ -545,6 +545,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
context.GetReservedStackOffset(),
isTail: true);
}
break;
case InstName.Ret:
@ -565,6 +566,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
context.TailMerger.AddUnconditionalReturn(writer, asm);
}
break;
case InstName.BCond:
@ -574,7 +576,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
case InstName.Tbz:
uint branchMask;
if (name == InstName.Tbnz || name == InstName.Tbz)
if (name is InstName.Tbnz or InstName.Tbz)
{
originalOffset = ImmUtils.ExtractSImm14Times4(encoding);
branchMask = 0x3fff;
@ -631,7 +633,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
{
delta = targetIndex - branchIndex;
if (delta >= -Encodable26BitsOffsetLimit && delta < Encodable26BitsOffsetLimit)
if (delta is >= (-Encodable26BitsOffsetLimit) and < Encodable26BitsOffsetLimit)
{
writer.WriteInstructionAt(branchIndex, (encoding & ~0x3ffffffu) | (uint)(delta & 0x3ffffff));
break;
@ -652,7 +654,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
case InstName.Tbz:
uint branchMask;
if (name == InstName.Tbnz || name == InstName.Tbz)
if (name is InstName.Tbnz or InstName.Tbz)
{
originalOffset = ImmUtils.ExtractSImm14Times4(encoding);
branchMask = 0x3fff;
@ -709,6 +711,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
writer.WriteInstructionAt(movedBranchIndex, (encoding & ~(branchMask << 5)) | (uint)((delta & branchMask) << 5));
WriteTailCallConstant(context, ref asm, blockIndex, targetAddress);
}
break;
default:

4
src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/Decoder.cs
View file

@ -72,7 +72,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
case InstName.Cbz:
case InstName.Tbnz:
case InstName.Tbz:
if (name == InstName.Tbnz || name == InstName.Tbz)
if (name is InstName.Tbnz or InstName.Tbz)
{
originalOffset = ImmUtils.ExtractSImm14Times4(encoding);
}
@ -369,7 +369,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
case InstName.Cbz:
case InstName.Tbnz:
case InstName.Tbz:
int imm = name == InstName.Tbnz || name == InstName.Tbz
int imm = name is InstName.Tbnz or InstName.Tbz
? ImmUtils.ExtractSImm14Times4(encoding)
: ImmUtils.ExtractSImm19Times4(encoding);

3
src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/InstEmitSystem.cs
View file

@ -230,7 +230,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
case InstName.Bl:
case InstName.Blr:
case InstName.Br:
if (name == InstName.BUncond || name == InstName.Bl)
if (name is InstName.BUncond or InstName.Bl)
{
int imm = ImmUtils.ExtractSImm26Times4(encoding);
@ -283,6 +283,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
isTail);
}
}
break;
default:

2
src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/InstTable.cs
View file

@ -451,7 +451,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
new(0x00000000, 0x20001000)
];
List<InstInfo> insts =
List<InstInfo> insts =
[
new(0x5AC02000, 0x7FFFFC00, InstName.Abs, IsaVersion.v89, InstFlags.RdRn),
new(0x5EE0B800, 0xFFFFFC00, InstName.AbsAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd),

6
src/Ryujinx.Cpu/LightningJit/Cache/JitCache.cs
View file

@ -150,7 +150,7 @@ namespace Ryujinx.Cpu.LightningJit.Cache
for (int i = _activeRegionIndex; i < _jitRegions.Count; i++)
{
int allocOffset = _cacheAllocator.Allocate(codeSize);
if (allocOffset >= 0)
{
_jitRegions[i].ExpandIfNeeded((ulong)allocOffset + (ulong)codeSize);
@ -163,11 +163,11 @@ namespace Ryujinx.Cpu.LightningJit.Cache
ReservedRegion newRegion = new(_jitRegions[0].Allocator, CacheSize);
_jitRegions.Add(newRegion);
_activeRegionIndex = _jitRegions.Count - 1;
int newRegionNumber = _activeRegionIndex;
Logger.Warning?.Print(LogClass.Cpu, $"JIT Cache Region {exhaustedRegion} exhausted, creating new Cache Region {newRegionNumber} ({((long)(newRegionNumber + 1) * CacheSize).Bytes()} Total Allocation).");
_cacheAllocator = new CacheMemoryAllocator(CacheSize);
int allocOffsetNew = _cacheAllocator.Allocate(codeSize);

1
src/Ryujinx.Cpu/LightningJit/CodeGen/Arm64/Assembler.cs
View file

@ -4360,6 +4360,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
instI |= 1 << 22; // sh flag
imm >>= 12;
}
WriteInstructionAuto(instI | (EncodeUImm12(imm, 0) << 10), rd, rn);
}
else

2
src/Ryujinx.Cpu/LightningJit/CodeGen/Arm64/CodeGenCommon.cs
View file

@ -28,7 +28,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
// Any value AND all ones will be equal itself, so it's effectively a no-op.
// Any value OR all ones will be equal all ones, so one can just use MOV.
// Any value XOR all ones will be equal its inverse, so one can just use MVN.
if (value == 0 || value == ulong.MaxValue)
if (value is 0 or ulong.MaxValue)
{
immN = 0;
immS = 0;

2
src/Ryujinx.Cpu/LightningJit/CodeGen/OperandType.cs
View file

@ -16,7 +16,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen
{
public static bool IsInteger(this OperandType type)
{
return type == OperandType.I32 || type == OperandType.I64;
return type is OperandType.I32 or OperandType.I64;
}
public static int GetSizeInBytes(this OperandType type)

2
src/Ryujinx.Cpu/LightningJit/Translator.cs
View file

@ -54,7 +54,7 @@ namespace Ryujinx.Cpu.LightningJit
}
}
private static IStackWalker CreateStackWalker()
private static StackWalker CreateStackWalker()
{
if (RuntimeInformation.ProcessArchitecture == Architecture.Arm64)
{

13
src/Ryujinx.Cpu/TickSource.cs
View file

@ -14,33 +14,30 @@ namespace Ryujinx.Cpu
/// <inheritdoc/>
public ulong Counter => (ulong)(ElapsedSeconds * Frequency);
public long TickScalar { get; set; }
public long TickScalar { get; set; }
private static long _acumElapsedTicks;
private static long _lastElapsedTicks;
private long ElapsedTicks
{
get
{
long elapsedTicks = _tickCounter.ElapsedTicks;
_acumElapsedTicks += (elapsedTicks - _lastElapsedTicks) * TickScalar / 100;
_lastElapsedTicks = elapsedTicks;
return _acumElapsedTicks;
}
}
/// <inheritdoc/>
public TimeSpan ElapsedTime => Stopwatch.GetElapsedTime(0, ElapsedTicks);
/// <inheritdoc/>