mirror of
https://git.ryujinx.app/ryubing/ryujinx.git
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Implement a new JIT for Arm devices (#6057)
* Implement a new JIT for Arm devices * Auto-format * Make a lot of Assembler members read-only * More read-only * Fix more warnings * ObjectDisposedException.ThrowIf * New JIT cache for platforms that enforce W^X, currently unused * Remove unused using * Fix assert * Pass memory manager type around * Safe memory manager mode support + other improvements * Actual safe memory manager mode masking support * PR feedback
This commit is contained in:
gdkchan
GitHub
parent
331c07807f
commit
427b7d06b5
135 changed files with 43322 additions and 24 deletions
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using Ryujinx.Cpu.LightningJit.CodeGen;
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using Ryujinx.Cpu.LightningJit.CodeGen.Arm64;
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using System;
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using System.Diagnostics;
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using System.Numerics;
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using System.Runtime.InteropServices;
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namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
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{
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static class InstEmitSystem
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{
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private delegate void SoftwareInterruptHandler(ulong address, int imm);
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private delegate ulong Get64();
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private delegate bool GetBool();
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private const int SpIndex = 31;
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public static void Bkpt(CodeGenContext context, uint imm)
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{
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context.AddPendingBkpt(imm);
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context.Arm64Assembler.B(0);
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}
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public static void Cps(CodeGenContext context, uint imod, uint m, uint a, uint i, uint f, uint mode)
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{
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// NOP in user mode.
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}
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public static void Dbg(CodeGenContext context, uint option)
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{
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// NOP in ARMv8.
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}
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public static void Hlt(CodeGenContext context, uint imm)
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{
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}
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public static void Mcr(CodeGenContext context, uint encoding, uint coproc, uint opc1, uint rt, uint crn, uint crm, uint opc2)
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{
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if (coproc != 15 || opc1 != 0)
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{
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Udf(context, encoding, 0);
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return;
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}
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Operand ctx = Register(context.RegisterAllocator.FixedContextRegister);
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Operand rtOperand = InstEmitCommon.GetInputGpr(context, rt);
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switch (crn)
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{
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case 13: // Process and Thread Info.
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if (crm == 0)
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{
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switch (opc2)
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{
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case 2:
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context.Arm64Assembler.StrRiUn(rtOperand, ctx, NativeContextOffsets.TpidrEl0Offset);
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return;
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}
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}
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break;
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}
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}
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public static void Mcrr(CodeGenContext context, uint encoding, uint coproc, uint opc1, uint rt, uint crm)
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{
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if (coproc != 15 || opc1 != 0)
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{
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Udf(context, encoding, 0);
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return;
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}
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// We don't have any system register that needs to be modified using a 64-bit value.
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}
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public static void Mrc(CodeGenContext context, uint encoding, uint coproc, uint opc1, uint rt, uint crn, uint crm, uint opc2)
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{
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if (coproc != 15 || opc1 != 0)
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{
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Udf(context, encoding, 0);
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return;
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}
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Operand ctx = Register(context.RegisterAllocator.FixedContextRegister);
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Operand rtOperand = InstEmitCommon.GetInputGpr(context, rt);
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bool hasValue = false;
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using ScopedRegister tempRegister = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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Operand dest = rt == RegisterUtils.PcRegister ? tempRegister.Operand : rtOperand;
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switch (crn)
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{
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case 13: // Process and Thread Info.
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if (crm == 0)
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{
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switch (opc2)
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{
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case 2:
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context.Arm64Assembler.LdrRiUn(dest, ctx, NativeContextOffsets.TpidrEl0Offset);
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hasValue = true;
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break;
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case 3:
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context.Arm64Assembler.LdrRiUn(dest, ctx, NativeContextOffsets.TpidrroEl0Offset);
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hasValue = true;
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break;
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}
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}
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break;
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}
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if (rt == RegisterUtils.PcRegister)
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{
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context.Arm64Assembler.MsrNzcv(dest);
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context.SetNzcvModified();
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}
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else if (!hasValue)
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{
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context.Arm64Assembler.Mov(dest, 0u);
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}
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}
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public static void Mrrc(CodeGenContext context, uint encoding, uint coproc, uint opc1, uint rt, uint rt2, uint crm)
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{
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if (coproc != 15)
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{
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Udf(context, encoding, 0);
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return;
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}
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switch (crm)
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{
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case 14:
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switch (opc1)
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{
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case 0:
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context.AddPendingReadCntpct(rt, rt2);
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context.Arm64Assembler.B(0);
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return;
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}
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break;
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}
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// Unsupported system register.
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context.Arm64Assembler.Mov(InstEmitCommon.GetOutputGpr(context, rt), 0u);
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context.Arm64Assembler.Mov(InstEmitCommon.GetOutputGpr(context, rt2), 0u);
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}
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public static void Mrs(CodeGenContext context, uint rd, bool r)
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{
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Operand rdOperand = InstEmitCommon.GetOutputGpr(context, rd);
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if (r)
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{
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// Reads SPSR, unpredictable in user mode.
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context.Arm64Assembler.Mov(rdOperand, 0u);
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}
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else
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{
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Operand ctx = Register(context.RegisterAllocator.FixedContextRegister);
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using ScopedRegister tempRegister = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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context.Arm64Assembler.LdrRiUn(tempRegister.Operand, ctx, NativeContextOffsets.FlagsBaseOffset);
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// Copy GE flags to destination register.
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context.Arm64Assembler.Ubfx(rdOperand, tempRegister.Operand, 16, 4);
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// Insert Q flag.
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context.Arm64Assembler.And(tempRegister.Operand, tempRegister.Operand, InstEmitCommon.Const(1 << 27));
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context.Arm64Assembler.Orr(rdOperand, rdOperand, tempRegister.Operand);
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// Insert NZCV flags.
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context.Arm64Assembler.MrsNzcv(tempRegister.Operand);
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context.Arm64Assembler.Orr(rdOperand, rdOperand, tempRegister.Operand);
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// All other flags can't be accessed in user mode or have "unknown" values.
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}
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}
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public static void MrsBr(CodeGenContext context, uint rd, uint m1, bool r)
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{
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Operand rdOperand = InstEmitCommon.GetOutputGpr(context, rd);
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// Reads banked register, unpredictable in user mode.
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context.Arm64Assembler.Mov(rdOperand, 0u);
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}
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public static void MsrBr(CodeGenContext context, uint rn, uint m1, bool r)
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{
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// Writes banked register, unpredictable in user mode.
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}
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public static void MsrI(CodeGenContext context, uint imm, uint mask, bool r)
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{
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if (r)
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{
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// Writes SPSR, unpredictable in user mode.
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}
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else
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{
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Operand ctx = Register(context.RegisterAllocator.FixedContextRegister);
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using ScopedRegister tempRegister = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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using ScopedRegister tempRegister2 = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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context.Arm64Assembler.LdrRiUn(tempRegister.Operand, ctx, NativeContextOffsets.FlagsBaseOffset);
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if ((mask & 2) != 0)
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{
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// Endian flag.
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context.Arm64Assembler.Mov(tempRegister2.Operand, (imm >> 9) & 1);
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context.Arm64Assembler.Bfi(tempRegister.Operand, tempRegister2.Operand, 9, 1);
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}
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if ((mask & 4) != 0)
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{
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// GE flags.
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context.Arm64Assembler.Mov(tempRegister2.Operand, (imm >> 16) & 0xf);
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context.Arm64Assembler.Bfi(tempRegister.Operand, tempRegister2.Operand, 16, 4);
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}
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if ((mask & 8) != 0)
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{
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// NZCVQ flags.
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context.Arm64Assembler.Mov(tempRegister2.Operand, (imm >> 27) & 0x1f);
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context.Arm64Assembler.Bfi(tempRegister.Operand, tempRegister2.Operand, 27, 5);
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context.Arm64Assembler.Mov(tempRegister2.Operand, (imm >> 28) & 0xf);
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InstEmitCommon.RestoreNzcvFlags(context, tempRegister2.Operand);
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context.SetNzcvModified();
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}
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}
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}
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public static void MsrR(CodeGenContext context, uint rn, uint mask, bool r)
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{
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Operand rnOperand = InstEmitCommon.GetInputGpr(context, rn);
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if (r)
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{
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// Writes SPSR, unpredictable in user mode.
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}
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else
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{
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Operand ctx = Register(context.RegisterAllocator.FixedContextRegister);
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using ScopedRegister tempRegister = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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using ScopedRegister tempRegister2 = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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context.Arm64Assembler.LdrRiUn(tempRegister.Operand, ctx, NativeContextOffsets.FlagsBaseOffset);
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if ((mask & 2) != 0)
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{
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// Endian flag.
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context.Arm64Assembler.Lsr(tempRegister2.Operand, rnOperand, InstEmitCommon.Const(9));
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context.Arm64Assembler.Bfi(tempRegister.Operand, tempRegister2.Operand, 9, 1);
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}
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if ((mask & 4) != 0)
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{
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// GE flags.
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context.Arm64Assembler.Lsr(tempRegister2.Operand, rnOperand, InstEmitCommon.Const(16));
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context.Arm64Assembler.Bfi(tempRegister.Operand, tempRegister2.Operand, 16, 4);
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}
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if ((mask & 8) != 0)
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{
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// NZCVQ flags.
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context.Arm64Assembler.Lsr(tempRegister2.Operand, rnOperand, InstEmitCommon.Const(27));
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context.Arm64Assembler.Bfi(tempRegister.Operand, tempRegister2.Operand, 27, 5);
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context.Arm64Assembler.Lsr(tempRegister2.Operand, rnOperand, InstEmitCommon.Const(28));
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InstEmitCommon.RestoreNzcvFlags(context, tempRegister2.Operand);
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context.SetNzcvModified();
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}
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}
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}
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public static void Setend(CodeGenContext context, bool e)
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{
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Operand ctx = Register(context.RegisterAllocator.FixedContextRegister);
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using ScopedRegister tempRegister = context.RegisterAllocator.AllocateTempGprRegisterScoped();
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context.Arm64Assembler.LdrRiUn(tempRegister.Operand, ctx, NativeContextOffsets.FlagsBaseOffset);
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if (e)
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{
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context.Arm64Assembler.Orr(tempRegister.Operand, tempRegister.Operand, InstEmitCommon.Const(1 << 9));
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}
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else
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{
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context.Arm64Assembler.Bfc(tempRegister.Operand, 9, 1);
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}
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context.Arm64Assembler.StrRiUn(tempRegister.Operand, ctx, NativeContextOffsets.FlagsBaseOffset);
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}
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public static void Svc(CodeGenContext context, uint imm)
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{
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context.AddPendingSvc(imm);
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context.Arm64Assembler.B(0);
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}
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public static void Udf(CodeGenContext context, uint encoding, uint imm)
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{
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context.AddPendingUdf(encoding);
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context.Arm64Assembler.B(0);
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}
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public static void PrivilegedInstruction(CodeGenContext context, uint encoding)
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{
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Udf(context, encoding, 0);
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}
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private static IntPtr GetBkptHandlerPtr()
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{
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return Marshal.GetFunctionPointerForDelegate<SoftwareInterruptHandler>(NativeInterface.Break);
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}
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private static IntPtr GetSvcHandlerPtr()
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{
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return Marshal.GetFunctionPointerForDelegate<SoftwareInterruptHandler>(NativeInterface.SupervisorCall);
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}
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private static IntPtr GetUdfHandlerPtr()
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{
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return Marshal.GetFunctionPointerForDelegate<SoftwareInterruptHandler>(NativeInterface.Undefined);
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}
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private static IntPtr GetCntpctEl0Ptr()
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{
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return Marshal.GetFunctionPointerForDelegate<Get64>(NativeInterface.GetCntpctEl0);
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}
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private static IntPtr CheckSynchronizationPtr()
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{
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return Marshal.GetFunctionPointerForDelegate<GetBool>(NativeInterface.CheckSynchronization);
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}
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public static bool NeedsCall(InstName name)
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{
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// All instructions that might do a host call should be included here.
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// That is required to reserve space on the stack for caller saved registers.
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switch (name)
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{
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case InstName.Mcr:
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case InstName.Mrc:
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case InstName.Mrrc:
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case InstName.Svc:
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case InstName.Udf:
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return true;
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}
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return false;
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}
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public static void WriteBkpt(CodeWriter writer, RegisterAllocator regAlloc, TailMerger tailMerger, int spillBaseOffset, uint pc, uint imm)
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{
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Assembler asm = new(writer);
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WriteCall(ref asm, regAlloc, GetBkptHandlerPtr(), skipContext: true, spillBaseOffset, null, pc, imm);
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WriteSyncPoint(writer, ref asm, regAlloc, tailMerger, skipContext: true, spillBaseOffset);
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}
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public static void WriteSvc(CodeWriter writer, RegisterAllocator regAlloc, TailMerger tailMerger, int spillBaseOffset, uint pc, uint svcId)
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{
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Assembler asm = new(writer);
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WriteCall(ref asm, regAlloc, GetSvcHandlerPtr(), skipContext: true, spillBaseOffset, null, pc, svcId);
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WriteSyncPoint(writer, ref asm, regAlloc, tailMerger, skipContext: true, spillBaseOffset);
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}
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public static void WriteUdf(CodeWriter writer, RegisterAllocator regAlloc, TailMerger tailMerger, int spillBaseOffset, uint pc, uint imm)
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{
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Assembler asm = new(writer);
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WriteCall(ref asm, regAlloc, GetUdfHandlerPtr(), skipContext: true, spillBaseOffset, null, pc, imm);
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WriteSyncPoint(writer, ref asm, regAlloc, tailMerger, skipContext: true, spillBaseOffset);
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}
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public static void WriteReadCntpct(CodeWriter writer, RegisterAllocator regAlloc, int spillBaseOffset, int rt, int rt2)
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{
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Assembler asm = new(writer);
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uint resultMask = (1u << rt) | (1u << rt2);
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int tempRegister = 0;
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while ((resultMask & (1u << tempRegister)) != 0 && tempRegister < 32)
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{
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tempRegister++;
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}
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Debug.Assert(tempRegister < 32);
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WriteSpill(ref asm, regAlloc, resultMask, skipContext: false, spillBaseOffset, tempRegister);
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Operand rn = Register(tempRegister);
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asm.Mov(rn, (ulong)GetCntpctEl0Ptr());
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asm.Blr(rn);
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if (rt != rt2)
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{
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asm.Lsr(Register(rt2), Register(0), InstEmitCommon.Const(32));
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}
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asm.Mov(Register(rt, OperandType.I32), Register(0, OperandType.I32)); // Zero-extend.
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WriteFill(ref asm, regAlloc, resultMask, skipContext: false, spillBaseOffset, tempRegister);
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}
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public static void WriteSyncPoint(CodeWriter writer, RegisterAllocator regAlloc, TailMerger tailMerger, int spillBaseOffset)
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{
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Assembler asm = new(writer);
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WriteSyncPoint(writer, ref asm, regAlloc, tailMerger, skipContext: false, spillBaseOffset);
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}
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private static void WriteSyncPoint(CodeWriter writer, ref Assembler asm, RegisterAllocator regAlloc, TailMerger tailMerger, bool skipContext, int spillBaseOffset)
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{
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int tempRegister = regAlloc.AllocateTempGprRegister();
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Operand rt = Register(tempRegister, OperandType.I32);
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asm.LdrRiUn(rt, Register(regAlloc.FixedContextRegister), NativeContextOffsets.CounterOffset);
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int branchIndex = writer.InstructionPointer;
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asm.Cbnz(rt, 0);
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WriteSpill(ref asm, regAlloc, 1u << tempRegister, skipContext, spillBaseOffset, tempRegister);
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Operand rn = Register(tempRegister == 0 ? 1 : 0);
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asm.Mov(rn, (ulong)CheckSynchronizationPtr());
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asm.Blr(rn);
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tailMerger.AddConditionalZeroReturn(writer, asm, Register(0, OperandType.I32));
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WriteFill(ref asm, regAlloc, 1u << tempRegister, skipContext, spillBaseOffset, tempRegister);
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asm.LdrRiUn(rt, Register(regAlloc.FixedContextRegister), NativeContextOffsets.CounterOffset);
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uint branchInst = writer.ReadInstructionAt(branchIndex);
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writer.WriteInstructionAt(branchIndex, branchInst | (((uint)(writer.InstructionPointer - branchIndex) & 0x7ffff) << 5));
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asm.Sub(rt, rt, new Operand(OperandKind.Constant, OperandType.I32, 1));
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asm.StrRiUn(rt, Register(regAlloc.FixedContextRegister), NativeContextOffsets.CounterOffset);
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regAlloc.FreeTempGprRegister(tempRegister);
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}
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private static void WriteCall(
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ref Assembler asm,
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RegisterAllocator regAlloc,
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IntPtr funcPtr,
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bool skipContext,
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int spillBaseOffset,
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int? resultRegister,
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params ulong[] callArgs)
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{
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uint resultMask = 0u;
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if (resultRegister.HasValue)
|
||||
{
|
||||
resultMask = 1u << resultRegister.Value;
|
||||
}
|
||||
|
||||
int tempRegister = callArgs.Length;
|
||||
|
||||
if (resultRegister.HasValue && tempRegister == resultRegister.Value)
|
||||
{
|
||||
tempRegister++;
|
||||
}
|
||||
|
||||
WriteSpill(ref asm, regAlloc, resultMask, skipContext, spillBaseOffset, tempRegister);
|
||||
|
||||
// We only support up to 7 arguments right now.
|
||||
// ABI defines the first 8 integer arguments to be passed on registers X0-X7.
|
||||
// We need at least one register to put the function address on, so that reduces the number of
|
||||
// registers we can use for that by one.
|
||||
|
||||
Debug.Assert(callArgs.Length < 8);
|
||||
|
||||
for (int index = 0; index < callArgs.Length; index++)
|
||||
{
|
||||
asm.Mov(Register(index), callArgs[index]);
|
||||
}
|
||||
|
||||
Operand rn = Register(tempRegister);
|
||||
|
||||
asm.Mov(rn, (ulong)funcPtr);
|
||||
asm.Blr(rn);
|
||||
|
||||
if (resultRegister.HasValue && resultRegister.Value != 0)
|
||||
{
|
||||
asm.Mov(Register(resultRegister.Value), Register(0));
|
||||
}
|
||||
|
||||
WriteFill(ref asm, regAlloc, resultMask, skipContext, spillBaseOffset, tempRegister);
|
||||
}
|
||||
|
||||
private static void WriteSpill(ref Assembler asm, RegisterAllocator regAlloc, uint exceptMask, bool skipContext, int spillOffset, int tempRegister)
|
||||
{
|
||||
WriteSpillOrFill(ref asm, regAlloc, skipContext, exceptMask, spillOffset, tempRegister, spill: true);
|
||||
}
|
||||
|
||||
private static void WriteFill(ref Assembler asm, RegisterAllocator regAlloc, uint exceptMask, bool skipContext, int spillOffset, int tempRegister)
|
||||
{
|
||||
WriteSpillOrFill(ref asm, regAlloc, skipContext, exceptMask, spillOffset, tempRegister, spill: false);
|
||||
}
|
||||
|
||||
private static void WriteSpillOrFill(
|
||||
ref Assembler asm,
|
||||
RegisterAllocator regAlloc,
|
||||
bool skipContext,
|
||||
uint exceptMask,
|
||||
int spillOffset,
|
||||
int tempRegister,
|
||||
bool spill)
|
||||
{
|
||||
uint gprMask = regAlloc.UsedGprsMask & ~(AbiConstants.GprCalleeSavedRegsMask | exceptMask);
|
||||
|
||||
if (skipContext)
|
||||
{
|
||||
gprMask &= ~Compiler.UsableGprsMask;
|
||||
}
|
||||
|
||||
if (!spill)
|
||||
{
|
||||
// We must reload the status register before reloading the GPRs,
|
||||
// since we might otherwise trash one of them by using it as temp register.
|
||||
|
||||
Operand rt = Register(tempRegister, OperandType.I32);
|
||||
|
||||
asm.LdrRiUn(rt, Register(SpIndex), spillOffset + BitOperations.PopCount(gprMask) * 8);
|
||||
asm.MsrNzcv(rt);
|
||||
}
|
||||
|
||||
while (gprMask != 0)
|
||||
{
|
||||
int reg = BitOperations.TrailingZeroCount(gprMask);
|
||||
|
||||
if (reg < 31 && (gprMask & (2u << reg)) != 0 && spillOffset < RegisterSaveRestore.Encodable9BitsOffsetLimit)
|
||||
{
|
||||
if (spill)
|
||||
{
|
||||
asm.StpRiUn(Register(reg), Register(reg + 1), Register(SpIndex), spillOffset);
|
||||
}
|
||||
else
|
||||
{
|
||||
asm.LdpRiUn(Register(reg), Register(reg + 1), Register(SpIndex), spillOffset);
|
||||
}
|
||||
|
||||
gprMask &= ~(3u << reg);
|
||||
spillOffset += 16;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (spill)
|
||||
{
|
||||
asm.StrRiUn(Register(reg), Register(SpIndex), spillOffset);
|
||||
}
|
||||
else
|
||||
{
|
||||
asm.LdrRiUn(Register(reg), Register(SpIndex), spillOffset);
|
||||
}
|
||||
|
||||
gprMask &= ~(1u << reg);
|
||||
spillOffset += 8;
|
||||
}
|
||||
}
|
||||
|
||||
if (spill)
|
||||
{
|
||||
Operand rt = Register(tempRegister, OperandType.I32);
|
||||
|
||||
asm.MrsNzcv(rt);
|
||||
asm.StrRiUn(rt, Register(SpIndex), spillOffset);
|
||||
}
|
||||
|
||||
spillOffset += 8;
|
||||
|
||||
if ((spillOffset & 8) != 0)
|
||||
{
|
||||
spillOffset += 8;
|
||||
}
|
||||
|
||||
uint fpSimdMask = regAlloc.UsedFpSimdMask;
|
||||
|
||||
if (skipContext)
|
||||
{
|
||||
fpSimdMask &= ~Compiler.UsableFpSimdMask;
|
||||
}
|
||||
|
||||
while (fpSimdMask != 0)
|
||||
{
|
||||
int reg = BitOperations.TrailingZeroCount(fpSimdMask);
|
||||
|
||||
if (reg < 31 && (fpSimdMask & (2u << reg)) != 0 && spillOffset < RegisterSaveRestore.Encodable9BitsOffsetLimit)
|
||||
{
|
||||
if (spill)
|
||||
{
|
||||
asm.StpRiUn(Register(reg, OperandType.V128), Register(reg + 1, OperandType.V128), Register(SpIndex), spillOffset);
|
||||
}
|
||||
else
|
||||
{
|
||||
asm.LdpRiUn(Register(reg, OperandType.V128), Register(reg + 1, OperandType.V128), Register(SpIndex), spillOffset);
|
||||
}
|
||||
|
||||
fpSimdMask &= ~(3u << reg);
|
||||
spillOffset += 32;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (spill)
|
||||
{
|
||||
asm.StrRiUn(Register(reg, OperandType.V128), Register(SpIndex), spillOffset);
|
||||
}
|
||||
else
|
||||
{
|
||||
asm.LdrRiUn(Register(reg, OperandType.V128), Register(SpIndex), spillOffset);
|
||||
}
|
||||
|
||||
fpSimdMask &= ~(1u << reg);
|
||||
spillOffset += 16;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
public static Operand Register(int register, OperandType type = OperandType.I64)
|
||||
{
|
||||
return new Operand(register, RegisterType.Integer, type);
|
||||
}
|
||||
}
|
||||
}
|
||||
Loading…
Add table
Add a link
Reference in a new issue