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Implement a new JIT for Arm devices (#6057)
* Implement a new JIT for Arm devices * Auto-format * Make a lot of Assembler members read-only * More read-only * Fix more warnings * ObjectDisposedException.ThrowIf * New JIT cache for platforms that enforce W^X, currently unused * Remove unused using * Fix assert * Pass memory manager type around * Safe memory manager mode support + other improvements * Actual safe memory manager mode masking support * PR feedback
This commit is contained in:
gdkchan
GitHub
parent
331c07807f
commit
427b7d06b5
135 changed files with 43322 additions and 24 deletions
495
src/Ryujinx.Cpu/LightningJit/Arm64/RegisterUtils.cs
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495
src/Ryujinx.Cpu/LightningJit/Arm64/RegisterUtils.cs
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using System.Diagnostics;
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namespace Ryujinx.Cpu.LightningJit.Arm64
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{
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static class RegisterUtils
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{
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private const int RdRtBit = 0;
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private const int RnBit = 5;
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private const int RmRsBit = 16;
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private const int RaRt2Bit = 10;
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// Some of those register have specific roles and can't be used as general purpose registers.
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// X18 - Reserved for platform specific usage.
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// X29 - Frame pointer.
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// X30 - Return address.
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// X31 - Not an actual register, in some cases maps to SP, and in others to ZR.
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public const uint ReservedRegsMask = (1u << 18) | (1u << 29) | (1u << 30) | (1u << 31);
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public const int LrIndex = 30;
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public const int SpIndex = 31;
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public const int ZrIndex = 31;
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public const int SpecialZrIndex = 32;
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public static uint RemapRegisters(RegisterAllocator regAlloc, InstFlags flags, uint encoding)
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{
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if (flags.HasFlag(InstFlags.Rd) && (!flags.HasFlag(InstFlags.FpSimd) || IsFpToGpr(flags, encoding)))
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{
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encoding = ReplaceGprRegister(regAlloc, encoding, RdRtBit, flags.HasFlag(InstFlags.RdSP));
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}
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if (flags.HasFlag(InstFlags.Rn) && (!flags.HasFlag(InstFlags.FpSimd) || IsFpFromGpr(flags, encoding) || flags.HasFlag(InstFlags.Memory)))
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{
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encoding = ReplaceGprRegister(regAlloc, encoding, RnBit, flags.HasFlag(InstFlags.RnSP));
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}
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if (!flags.HasFlag(InstFlags.FpSimd))
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{
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if (flags.HasFlag(InstFlags.Rm) || flags.HasFlag(InstFlags.Rs))
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{
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encoding = ReplaceGprRegister(regAlloc, encoding, RmRsBit);
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}
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if (flags.HasFlag(InstFlags.Ra) || flags.HasFlag(InstFlags.Rt2))
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{
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encoding = ReplaceGprRegister(regAlloc, encoding, RaRt2Bit);
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}
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if (flags.HasFlag(InstFlags.Rt))
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{
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encoding = ReplaceGprRegister(regAlloc, encoding, RdRtBit);
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}
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}
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else if (flags.HasFlag(InstFlags.Rm) && flags.HasFlag(InstFlags.Memory))
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{
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encoding = ReplaceGprRegister(regAlloc, encoding, RmRsBit);
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}
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return encoding;
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}
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public static uint ReplaceRt(uint encoding, int newIndex)
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{
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return ReplaceRegister(encoding, newIndex, RdRtBit);
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}
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public static uint ReplaceRn(uint encoding, int newIndex)
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{
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return ReplaceRegister(encoding, newIndex, RnBit);
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}
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private static uint ReplaceRegister(uint encoding, int newIndex, int bit)
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{
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encoding &= ~(0x1fu << bit);
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encoding |= (uint)newIndex << bit;
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return encoding;
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}
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private static uint ReplaceGprRegister(RegisterAllocator regAlloc, uint encoding, int bit, bool hasSP = false)
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{
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int oldIndex = (int)(encoding >> bit) & 0x1f;
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if (oldIndex == ZrIndex && !hasSP)
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{
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return encoding;
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}
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int newIndex = regAlloc.RemapReservedGprRegister(oldIndex);
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encoding &= ~(0x1fu << bit);
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encoding |= (uint)newIndex << bit;
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return encoding;
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}
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public static (uint, uint) PopulateReadMasks(InstName name, InstFlags flags, uint encoding)
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{
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uint gprMask = 0;
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uint fpSimdMask = 0;
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if (flags.HasFlag(InstFlags.FpSimd))
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{
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if (flags.HasFlag(InstFlags.Rd) && flags.HasFlag(InstFlags.ReadRd))
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{
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uint mask = MaskFromIndex(ExtractRd(flags, encoding));
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if (IsFpToGpr(flags, encoding))
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{
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gprMask |= mask;
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}
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else
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{
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fpSimdMask |= mask;
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}
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}
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if (flags.HasFlag(InstFlags.Rn))
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{
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uint mask = MaskFromIndex(ExtractRn(flags, encoding));
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if (flags.HasFlag(InstFlags.RnSeq))
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{
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int count = GetRnSequenceCount(encoding);
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for (int index = 0; index < count; index++, mask <<= 1)
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{
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fpSimdMask |= mask;
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}
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}
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else if (IsFpFromGpr(flags, encoding) || flags.HasFlag(InstFlags.Memory))
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{
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gprMask |= mask;
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}
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else
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{
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fpSimdMask |= mask;
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}
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}
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if (flags.HasFlag(InstFlags.Rm))
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{
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uint mask = MaskFromIndex(ExtractRm(flags, encoding));
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if (flags.HasFlag(InstFlags.Memory))
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{
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gprMask |= mask;
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}
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else
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{
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fpSimdMask |= mask;
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}
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}
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if (flags.HasFlag(InstFlags.Ra))
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{
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fpSimdMask |= MaskFromIndex(ExtractRa(flags, encoding));
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}
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if (flags.HasFlag(InstFlags.ReadRt))
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{
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if (flags.HasFlag(InstFlags.Rt))
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{
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uint mask = MaskFromIndex(ExtractRt(flags, encoding));
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if (flags.HasFlag(InstFlags.RtSeq))
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{
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int count = GetRtSequenceCount(name, encoding);
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for (int index = 0; index < count; index++, mask <<= 1)
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{
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fpSimdMask |= mask;
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}
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}
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else
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{
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fpSimdMask |= mask;
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}
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}
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if (flags.HasFlag(InstFlags.Rt2))
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{
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fpSimdMask |= MaskFromIndex(ExtractRt2(flags, encoding));
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}
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}
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}
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else
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{
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if (flags.HasFlag(InstFlags.Rd) && flags.HasFlag(InstFlags.ReadRd))
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{
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gprMask |= MaskFromIndex(ExtractRd(flags, encoding));
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}
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if (flags.HasFlag(InstFlags.Rn))
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{
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gprMask |= MaskFromIndex(ExtractRn(flags, encoding));
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}
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if (flags.HasFlag(InstFlags.Rm))
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{
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gprMask |= MaskFromIndex(ExtractRm(flags, encoding));
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}
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if (flags.HasFlag(InstFlags.Ra))
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{
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gprMask |= MaskFromIndex(ExtractRa(flags, encoding));
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}
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if (flags.HasFlag(InstFlags.ReadRt))
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{
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if (flags.HasFlag(InstFlags.Rt))
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{
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gprMask |= MaskFromIndex(ExtractRt(flags, encoding));
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}
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if (flags.HasFlag(InstFlags.Rt2))
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{
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gprMask |= MaskFromIndex(ExtractRt2(flags, encoding));
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}
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}
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}
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return (gprMask, fpSimdMask);
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}
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public static (uint, uint) PopulateWriteMasks(InstName name, InstFlags flags, uint encoding)
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{
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uint gprMask = 0;
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uint fpSimdMask = 0;
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if (flags.HasFlag(InstFlags.MemWBack))
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{
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gprMask |= MaskFromIndex(ExtractRn(flags, encoding));
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}
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if (flags.HasFlag(InstFlags.FpSimd))
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{
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if (flags.HasFlag(InstFlags.Rd))
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{
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uint mask = MaskFromIndex(ExtractRd(flags, encoding));
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if (IsFpToGpr(flags, encoding))
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{
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gprMask |= mask;
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}
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else
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{
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fpSimdMask |= mask;
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}
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}
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if (!flags.HasFlag(InstFlags.ReadRt))
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{
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if (flags.HasFlag(InstFlags.Rt))
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{
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uint mask = MaskFromIndex(ExtractRt(flags, encoding));
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if (flags.HasFlag(InstFlags.RtSeq))
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{
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int count = GetRtSequenceCount(name, encoding);
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for (int index = 0; index < count; index++, mask <<= 1)
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{
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fpSimdMask |= mask;
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}
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}
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else
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{
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fpSimdMask |= mask;
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}
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}
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if (flags.HasFlag(InstFlags.Rt2))
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{
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fpSimdMask |= MaskFromIndex(ExtractRt2(flags, encoding));
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}
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}
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}
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else
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{
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if (flags.HasFlag(InstFlags.Rd))
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{
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gprMask |= MaskFromIndex(ExtractRd(flags, encoding));
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}
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if (!flags.HasFlag(InstFlags.ReadRt))
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{
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if (flags.HasFlag(InstFlags.Rt))
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{
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gprMask |= MaskFromIndex(ExtractRt(flags, encoding));
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}
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if (flags.HasFlag(InstFlags.Rt2))
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{
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gprMask |= MaskFromIndex(ExtractRt2(flags, encoding));
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}
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}
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if (flags.HasFlag(InstFlags.Rs))
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{
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gprMask |= MaskFromIndex(ExtractRs(flags, encoding));
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}
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}
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return (gprMask, fpSimdMask);
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}
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private static uint MaskFromIndex(int index)
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{
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if (index < SpecialZrIndex)
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{
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return 1u << index;
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}
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return 0u;
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}
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private static bool IsFpFromGpr(InstFlags flags, uint encoding)
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{
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InstFlags bothFlags = InstFlags.FpSimdFromGpr | InstFlags.FpSimdToGpr;
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if ((flags & bothFlags) == bothFlags) // FMOV (general)
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{
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return (encoding & (1u << 16)) != 0;
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}
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return flags.HasFlag(InstFlags.FpSimdFromGpr);
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}
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private static bool IsFpToGpr(InstFlags flags, uint encoding)
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{
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InstFlags bothFlags = InstFlags.FpSimdFromGpr | InstFlags.FpSimdToGpr;
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if ((flags & bothFlags) == bothFlags) // FMOV (general)
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{
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return (encoding & (1u << 16)) == 0;
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}
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return flags.HasFlag(InstFlags.FpSimdToGpr);
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}
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private static int GetRtSequenceCount(InstName name, uint encoding)
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{
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switch (name)
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{
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case InstName.Ld1AdvsimdMultAsNoPostIndex:
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case InstName.Ld1AdvsimdMultAsPostIndex:
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case InstName.St1AdvsimdMultAsNoPostIndex:
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case InstName.St1AdvsimdMultAsPostIndex:
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return ((encoding >> 12) & 0xf) switch
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{
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0b0000 => 4,
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0b0010 => 4,
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0b0100 => 3,
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0b0110 => 3,
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0b0111 => 1,
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0b1000 => 2,
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0b1010 => 2,
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_ => 1,
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};
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case InstName.Ld1rAdvsimdAsNoPostIndex:
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case InstName.Ld1rAdvsimdAsPostIndex:
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case InstName.Ld1AdvsimdSnglAsNoPostIndex:
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case InstName.Ld1AdvsimdSnglAsPostIndex:
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case InstName.St1AdvsimdSnglAsNoPostIndex:
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case InstName.St1AdvsimdSnglAsPostIndex:
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return 1;
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case InstName.Ld2rAdvsimdAsNoPostIndex:
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case InstName.Ld2rAdvsimdAsPostIndex:
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case InstName.Ld2AdvsimdMultAsNoPostIndex:
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case InstName.Ld2AdvsimdMultAsPostIndex:
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case InstName.Ld2AdvsimdSnglAsNoPostIndex:
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case InstName.Ld2AdvsimdSnglAsPostIndex:
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case InstName.St2AdvsimdMultAsNoPostIndex:
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case InstName.St2AdvsimdMultAsPostIndex:
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case InstName.St2AdvsimdSnglAsNoPostIndex:
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case InstName.St2AdvsimdSnglAsPostIndex:
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return 2;
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case InstName.Ld3rAdvsimdAsNoPostIndex:
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case InstName.Ld3rAdvsimdAsPostIndex:
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case InstName.Ld3AdvsimdMultAsNoPostIndex:
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case InstName.Ld3AdvsimdMultAsPostIndex:
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case InstName.Ld3AdvsimdSnglAsNoPostIndex:
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case InstName.Ld3AdvsimdSnglAsPostIndex:
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case InstName.St3AdvsimdMultAsNoPostIndex:
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case InstName.St3AdvsimdMultAsPostIndex:
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case InstName.St3AdvsimdSnglAsNoPostIndex:
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case InstName.St3AdvsimdSnglAsPostIndex:
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return 3;
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case InstName.Ld4rAdvsimdAsNoPostIndex:
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case InstName.Ld4rAdvsimdAsPostIndex:
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case InstName.Ld4AdvsimdMultAsNoPostIndex:
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case InstName.Ld4AdvsimdMultAsPostIndex:
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case InstName.Ld4AdvsimdSnglAsNoPostIndex:
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case InstName.Ld4AdvsimdSnglAsPostIndex:
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case InstName.St4AdvsimdMultAsNoPostIndex:
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case InstName.St4AdvsimdMultAsPostIndex:
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case InstName.St4AdvsimdSnglAsNoPostIndex:
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case InstName.St4AdvsimdSnglAsPostIndex:
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return 4;
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}
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return 1;
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}
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private static int GetRnSequenceCount(uint encoding)
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{
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return ((int)(encoding >> 13) & 3) + 1;
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}
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public static int ExtractRd(InstFlags flags, uint encoding)
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{
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Debug.Assert(flags.HasFlag(InstFlags.Rd));
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int index = (int)(encoding >> RdRtBit) & 0x1f;
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if (!flags.HasFlag(InstFlags.RdSP) && index == ZrIndex)
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{
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return SpecialZrIndex;
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}
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return index;
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}
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public static int ExtractRn(uint encoding)
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{
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return (int)(encoding >> RnBit) & 0x1f;
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}
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public static int ExtractRn(InstFlags flags, uint encoding)
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{
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Debug.Assert(flags.HasFlag(InstFlags.Rn));
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int index = ExtractRn(encoding);
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if (!flags.HasFlag(InstFlags.RnSP) && index == ZrIndex)
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{
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return SpecialZrIndex;
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}
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return index;
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}
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public static int ExtractRm(uint encoding)
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{
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return (int)(encoding >> RmRsBit) & 0x1f;
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}
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public static int ExtractRm(InstFlags flags, uint encoding)
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{
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Debug.Assert(flags.HasFlag(InstFlags.Rm));
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int index = ExtractRm(encoding);
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return index == ZrIndex ? SpecialZrIndex : index;
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}
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public static int ExtractRs(uint encoding)
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{
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return (int)(encoding >> RmRsBit) & 0x1f;
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}
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public static int ExtractRs(InstFlags flags, uint encoding)
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{
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Debug.Assert(flags.HasFlag(InstFlags.Rs));
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int index = ExtractRs(encoding);
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return index == ZrIndex ? SpecialZrIndex : index;
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}
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public static int ExtractRa(InstFlags flags, uint encoding)
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{
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Debug.Assert(flags.HasFlag(InstFlags.Ra));
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int index = (int)(encoding >> RaRt2Bit) & 0x1f;
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return index == ZrIndex ? SpecialZrIndex : index;
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}
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public static int ExtractRt(uint encoding)
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{
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return (int)(encoding >> RdRtBit) & 0x1f;
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}
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public static int ExtractRt(InstFlags flags, uint encoding)
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{
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Debug.Assert(flags.HasFlag(InstFlags.Rt));
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int index = ExtractRt(encoding);
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return index == ZrIndex ? SpecialZrIndex : index;
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}
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public static int ExtractRt2(InstFlags flags, uint encoding)
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{
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Debug.Assert(flags.HasFlag(InstFlags.Rt2));
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int index = (int)(encoding >> RaRt2Bit) & 0x1f;
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return index == ZrIndex ? SpecialZrIndex : index;
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}
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}
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}
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