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misc: chore: Use explicit types in CPU project

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This commit is contained in:
Evan Husted 2025-01-25 14:04:43 -06:00
parent a97fd4beb1
commit 5099548856
18 changed files with 40 additions and 40 deletions
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10
src/Ryujinx.Cpu/LightningJit/CodeGen/Arm64/Assembler.cs
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@ -41,7 +41,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
{
int targetIndex = _code.Count;
var state = _labels[label.AsInt32()];
LabelState state = _labels[label.AsInt32()];
state.TargetIndex = targetIndex;
state.HasTarget = true;
@ -68,7 +68,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
{
int branchIndex = _code.Count;
var state = _labels[label.AsInt32()];
LabelState state = _labels[label.AsInt32()];
state.BranchIndex = branchIndex;
state.HasBranch = true;
@ -94,7 +94,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
{
int branchIndex = _code.Count;
var state = _labels[label.AsInt32()];
LabelState state = _labels[label.AsInt32()];
state.BranchIndex = branchIndex;
state.HasBranch = true;
@ -113,7 +113,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
{
int branchIndex = _code.Count;
var state = _labels[label.AsInt32()];
LabelState state = _labels[label.AsInt32()];
state.BranchIndex = branchIndex;
state.HasBranch = true;
@ -342,7 +342,7 @@ namespace Ryujinx.Cpu.LightningJit.CodeGen.Arm64
public readonly void Cset(Operand rd, ArmCondition condition)
{
var zr = new Operand(ZrRegister, RegisterType.Integer, rd.Type);
Operand zr = new Operand(ZrRegister, RegisterType.Integer, rd.Type);
Csinc(rd, zr, zr, (ArmCondition)((int)condition ^ 1));
}