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Implement UQADD16, UQADD8, UQSUB16, UQSUB8, VQRDMULH, VSLI and VSWP Arm32 instructions (#7174)
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gdkchan
GitHub
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commit
8d8983049e
12 changed files with 445 additions and 13 deletions
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@ -2,6 +2,8 @@ using ARMeilleure.Decoders;
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using ARMeilleure.IntermediateRepresentation;
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using ARMeilleure.State;
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using ARMeilleure.Translation;
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using System;
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using System.Diagnostics;
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using System.Diagnostics.CodeAnalysis;
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using static ARMeilleure.Instructions.InstEmitAluHelper;
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using static ARMeilleure.Instructions.InstEmitHelper;
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@ -558,6 +560,46 @@ namespace ARMeilleure.Instructions
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EmitHsub8(context, unsigned: true);
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}
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public static void Uqadd16(ArmEmitterContext context)
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{
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OpCode32AluReg op = (OpCode32AluReg)context.CurrOp;
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SetIntA32(context, op.Rd, EmitUnsigned16BitPair(context, GetIntA32(context, op.Rn), GetIntA32(context, op.Rm), (d, n, m) =>
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{
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EmitSaturateUqadd(context, d, context.Add(n, m), 16);
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}));
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}
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public static void Uqadd8(ArmEmitterContext context)
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{
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OpCode32AluReg op = (OpCode32AluReg)context.CurrOp;
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SetIntA32(context, op.Rd, EmitUnsigned8BitPair(context, GetIntA32(context, op.Rn), GetIntA32(context, op.Rm), (d, n, m) =>
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{
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EmitSaturateUqadd(context, d, context.Add(n, m), 8);
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}));
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}
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public static void Uqsub16(ArmEmitterContext context)
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{
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OpCode32AluReg op = (OpCode32AluReg)context.CurrOp;
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SetIntA32(context, op.Rd, EmitUnsigned16BitPair(context, GetIntA32(context, op.Rn), GetIntA32(context, op.Rm), (d, n, m) =>
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{
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EmitSaturateUqsub(context, d, context.Subtract(n, m), 16);
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}));
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}
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public static void Uqsub8(ArmEmitterContext context)
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{
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OpCode32AluReg op = (OpCode32AluReg)context.CurrOp;
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SetIntA32(context, op.Rd, EmitUnsigned8BitPair(context, GetIntA32(context, op.Rn), GetIntA32(context, op.Rm), (d, n, m) =>
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{
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EmitSaturateUqsub(context, d, context.Subtract(n, m), 8);
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}));
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}
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public static void Usat(ArmEmitterContext context)
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{
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OpCode32Sat op = (OpCode32Sat)context.CurrOp;
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@ -934,6 +976,148 @@ namespace ARMeilleure.Instructions
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}
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}
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private static void EmitSaturateUqadd(ArmEmitterContext context, Operand result, Operand value, uint saturateTo)
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{
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Debug.Assert(saturateTo <= 32);
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if (saturateTo == 32)
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{
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// No saturation possible for this case.
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context.Copy(result, value);
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return;
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}
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else if (saturateTo == 0)
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{
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// Result is always zero if we saturate 0 bits.
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context.Copy(result, Const(0));
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return;
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}
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// If the result is 0, the values are equal and we don't need saturation.
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Operand lblNoSat = Label();
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context.BranchIfFalse(lblNoSat, context.ShiftRightUI(value, Const((int)saturateTo)));
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// Saturate.
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context.Copy(result, Const(uint.MaxValue >> (32 - (int)saturateTo)));
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Operand lblExit = Label();
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context.Branch(lblExit);
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context.MarkLabel(lblNoSat);
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context.Copy(result, value);
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context.MarkLabel(lblExit);
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}
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private static void EmitSaturateUqsub(ArmEmitterContext context, Operand result, Operand value, uint saturateTo)
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{
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Debug.Assert(saturateTo <= 32);
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if (saturateTo == 32)
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{
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// No saturation possible for this case.
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context.Copy(result, value);
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return;
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}
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else if (saturateTo == 0)
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{
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// Result is always zero if we saturate 0 bits.
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context.Copy(result, Const(0));
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return;
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}
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// If the result is 0, the values are equal and we don't need saturation.
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Operand lblNoSat = Label();
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context.BranchIf(lblNoSat, value, Const(0), Comparison.GreaterOrEqual);
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// Saturate.
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// Assumes that the value can only underflow, since this is only used for unsigned subtraction.
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context.Copy(result, Const(0));
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Operand lblExit = Label();
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context.Branch(lblExit);
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context.MarkLabel(lblNoSat);
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context.Copy(result, value);
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context.MarkLabel(lblExit);
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}
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private static Operand EmitUnsigned16BitPair(ArmEmitterContext context, Operand rn, Operand rm, Action<Operand, Operand, Operand> elementAction)
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{
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Operand tempD = context.AllocateLocal(OperandType.I32);
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Operand tempN = context.ZeroExtend16(OperandType.I32, rn);
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Operand tempM = context.ZeroExtend16(OperandType.I32, rm);
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elementAction(tempD, tempN, tempM);
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Operand tempD2 = context.ZeroExtend16(OperandType.I32, tempD);
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tempN = context.ShiftRightUI(rn, Const(16));
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tempM = context.ShiftRightUI(rm, Const(16));
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elementAction(tempD, tempN, tempM);
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return context.BitwiseOr(tempD2, context.ShiftLeft(tempD, Const(16)));
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}
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private static Operand EmitSigned8BitPair(ArmEmitterContext context, Operand rn, Operand rm, Action<Operand, Operand, Operand> elementAction)
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{
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return Emit8BitPair(context, rn, rm, elementAction, unsigned: false);
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}
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private static Operand EmitUnsigned8BitPair(ArmEmitterContext context, Operand rn, Operand rm, Action<Operand, Operand, Operand> elementAction)
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{
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return Emit8BitPair(context, rn, rm, elementAction, unsigned: true);
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}
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private static Operand Emit8BitPair(ArmEmitterContext context, Operand rn, Operand rm, Action<Operand, Operand, Operand> elementAction, bool unsigned)
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{
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Operand tempD = context.AllocateLocal(OperandType.I32);
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Operand result = default;
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for (int b = 0; b < 4; b++)
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{
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Operand nByte = b != 0 ? context.ShiftRightUI(rn, Const(b * 8)) : rn;
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Operand mByte = b != 0 ? context.ShiftRightUI(rm, Const(b * 8)) : rm;
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if (unsigned)
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{
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nByte = context.ZeroExtend8(OperandType.I32, nByte);
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mByte = context.ZeroExtend8(OperandType.I32, mByte);
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}
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else
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{
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nByte = context.SignExtend8(OperandType.I32, nByte);
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mByte = context.SignExtend8(OperandType.I32, mByte);
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}
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elementAction(tempD, nByte, mByte);
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if (b == 0)
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{
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result = context.ZeroExtend8(OperandType.I32, tempD);
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}
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else if (b < 3)
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{
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result = context.BitwiseOr(result, context.ShiftLeft(context.ZeroExtend8(OperandType.I32, tempD), Const(b * 8)));
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}
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else
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{
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result = context.BitwiseOr(result, context.ShiftLeft(tempD, Const(24)));
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}
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}
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return result;
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}
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private static void EmitAluStore(ArmEmitterContext context, Operand value)
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{
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IOpCode32Alu op = (IOpCode32Alu)context.CurrOp;
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@ -1246,6 +1246,33 @@ namespace ARMeilleure.Instructions
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EmitVectorUnaryNarrowOp32(context, (op1) => EmitSatQ(context, op1, 8 << op.Size, signedSrc: true, signedDst: false), signed: true);
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}
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public static void Vqrdmulh(ArmEmitterContext context)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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int eSize = 8 << op.Size;
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EmitVectorBinaryOpI32(context, (op1, op2) =>
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{
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if (op.Size == 2)
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{
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op1 = context.SignExtend32(OperandType.I64, op1);
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op2 = context.SignExtend32(OperandType.I64, op2);
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}
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Operand res = context.Multiply(op1, op2);
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res = context.Add(res, Const(res.Type, 1L << (eSize - 2)));
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res = context.ShiftRightSI(res, Const(eSize - 1));
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res = EmitSatQ(context, res, eSize, signedSrc: true, signedDst: true);
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if (op.Size == 2)
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{
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res = context.ConvertI64ToI32(res);
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}
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return res;
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}, signed: true);
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}
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public static void Vqsub(ArmEmitterContext context)
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{
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OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
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@ -191,6 +191,26 @@ namespace ARMeilleure.Instructions
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void Vswp(ArmEmitterContext context)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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if (op.Q)
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{
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Operand temp = context.Copy(GetVecA32(op.Qd));
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context.Copy(GetVecA32(op.Qd), GetVecA32(op.Qm));
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context.Copy(GetVecA32(op.Qm), temp);
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}
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else
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{
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Operand temp = ExtractScalar(context, OperandType.I64, op.Vd);
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InsertScalar(context, op.Vd, ExtractScalar(context, OperandType.I64, op.Vm));
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InsertScalar(context, op.Vm, temp);
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}
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}
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public static void Vtbl(ArmEmitterContext context)
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{
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OpCode32SimdTbl op = (OpCode32SimdTbl)context.CurrOp;
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@ -130,6 +130,36 @@ namespace ARMeilleure.Instructions
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EmitVectorUnaryNarrowOp32(context, (op1) => context.ShiftRightUI(op1, Const(shift)));
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}
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public static void Vsli_I(ArmEmitterContext context)
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{
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OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp;
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int shift = op.Shift;
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int eSize = 8 << op.Size;
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ulong mask = shift != 0 ? ulong.MaxValue >> (64 - shift) : 0UL;
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Operand res = GetVec(op.Qd);
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int elems = op.GetBytesCount() >> op.Size;
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for (int index = 0; index < elems; index++)
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{
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Operand me = EmitVectorExtractZx(context, op.Qm, op.Im + index, op.Size);
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Operand neShifted = context.ShiftLeft(me, Const(shift));
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Operand de = EmitVectorExtractZx(context, op.Qd, op.Id + index, op.Size);
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Operand deMasked = context.BitwiseAnd(de, Const(mask));
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Operand e = context.BitwiseOr(neShifted, deMasked);
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res = EmitVectorInsert(context, res, e, op.Id + index, op.Size);
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}
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context.Copy(GetVec(op.Qd), res);
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}
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public static void Vsra(ArmEmitterContext context)
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{
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OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp;
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@ -571,6 +571,10 @@ namespace ARMeilleure.Instructions
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Umaal,
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Umlal,
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Umull,
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Uqadd16,
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Uqadd8,
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Uqsub16,
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Uqsub8,
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Usat,
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Usat16,
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Usub8,
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@ -645,6 +649,7 @@ namespace ARMeilleure.Instructions
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Vqdmulh,
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Vqmovn,
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Vqmovun,
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Vqrdmulh,
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Vqrshrn,
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Vqrshrun,
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Vqshrn,
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@ -666,6 +671,7 @@ namespace ARMeilleure.Instructions
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Vshll,
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Vshr,
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Vshrn,
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Vsli,
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Vst1,
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Vst2,
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Vst3,
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@ -682,6 +688,7 @@ namespace ARMeilleure.Instructions
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Vsub,
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Vsubl,
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Vsubw,
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Vswp,
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Vtbl,
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Vtrn,
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Vtst,
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