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Implement UQADD16, UQADD8, UQSUB16, UQSUB8, VQRDMULH, VSLI and VSWP Arm32 instructions (#7174)

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gdkchan 2024-08-08 17:07:24 -03:00 • committed by GitHub
parent 7969fb6bba
commit 8d8983049e
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12 changed files with 445 additions and 13 deletions
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26
src/Ryujinx.Tests/Cpu/CpuTestSimd32.cs
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@ -327,6 +327,32 @@ namespace Ryujinx.Tests.Cpu
CompareAgainstUnicorn();
}
[Test, Pairwise, Description("VSWP D0, D0")]
public void Vswp([Values(0u, 1u)] uint rd,
[Values(0u, 1u)] uint rm,
[Values] bool q)
{
uint opcode = 0xf3b20000u; // VSWP D0, D0
if (q)
{
opcode |= 1u << 6;
rd &= ~1u;
rm &= ~1u;
}
opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
V128 v0 = new(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
V128 v1 = new(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong());
SingleOpcode(opcode, v0: v0, v1: v1);
CompareAgainstUnicorn();
}
#endif
}
}