crafterpika/ryujinx
1
0
Fork 0
mirror of https://git.ryujinx.app/ryubing/ryujinx.git synced 2025-07-20 15:47:10 +02:00
Code Issues Projects Releases Packages Wiki Activity

some more extension members

Browse source
This commit is contained in:
GreemDev 2025-07-02 15:02:04 -05:00
parent 3311842a16
commit a53de86a19
6 changed files with 38 additions and 125 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/Ryujinx.Cpu/LightningJit/Arm64/Block.cs
View file

@ -132,7 +132,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64
InstName lastInstructionName = Instructions[^1].Name;
return lastInstructionName.IsCall() || lastInstructionName.IsException();
return lastInstructionName.IsCall || lastInstructionName.IsException;
}
}
}

139
src/Ryujinx.Cpu/LightningJit/Arm64/InstName.cs
View file

@ -1042,126 +1042,39 @@ namespace Ryujinx.Cpu.LightningJit.Arm64
static class InstNameExtensions
{
public static bool IsCall(this InstName name)
extension(InstName name)
{
return name is InstName.Bl or InstName.Blr;
}
public bool IsCall => name is InstName.Bl or InstName.Blr;
public static bool IsControlFlowOrException(this InstName name)
{
switch (name)
public bool IsControlFlowOrException => name is
InstName.BUncond or InstName.BCond or InstName.Bl or InstName.Blr or InstName.Br or InstName.Brk
or InstName.Cbnz or InstName.Cbz or InstName.Ret or InstName.Tbnz or InstName.Tbz or InstName.Svc
or InstName.UdfPermUndef;
public bool IsException => name is InstName.Brk or InstName.Svc or InstName.UdfPermUndef;
public bool IsSystem => name switch
{
case InstName.BUncond:
case InstName.BCond:
case InstName.Bl:
case InstName.Blr:
case InstName.Br:
case InstName.Brk:
case InstName.Cbnz:
case InstName.Cbz:
case InstName.Ret:
case InstName.Tbnz:
case InstName.Tbz:
case InstName.Svc:
case InstName.UdfPermUndef:
return true;
}
InstName.Mrs or InstName.MsrImm or InstName.MsrReg => true,
_ => name.IsException
};
return false;
}
public bool IsSystemOrCall => name.IsCall || name is
InstName.Svc or InstName.Mrs or InstName.MsrImm or InstName.MsrReg
or InstName.Sysl;
public static bool IsException(this InstName name)
{
switch (name)
{
case InstName.Brk:
case InstName.Svc:
case InstName.UdfPermUndef:
return true;
}
public bool IsPrivileged => name is
InstName.Dcps1 or InstName.Dcps2 or InstName.Dcps3 or InstName.Drps or InstName.Eret or InstName.Ereta
or InstName.Hvc or InstName.MsrImm or InstName.Smc;
return false;
}
public bool IsPartialRegisterUpdateMemory => name is
InstName.Ld1AdvsimdSnglAsNoPostIndex or InstName.Ld1AdvsimdSnglAsPostIndex
or InstName.Ld2AdvsimdSnglAsNoPostIndex or InstName.Ld2AdvsimdSnglAsPostIndex
or InstName.Ld3AdvsimdSnglAsNoPostIndex or InstName.Ld3AdvsimdSnglAsPostIndex
or InstName.Ld4AdvsimdSnglAsNoPostIndex or InstName.Ld4AdvsimdSnglAsPostIndex;
public static bool IsSystem(this InstName name)
{
switch (name)
{
case InstName.Mrs:
case InstName.MsrImm:
case InstName.MsrReg:
return true;
}
return name.IsException();
}
public static bool IsSystemOrCall(this InstName name)
{
switch (name)
{
case InstName.Bl:
case InstName.Blr:
case InstName.Svc:
case InstName.Mrs:
case InstName.MsrImm:
case InstName.MsrReg:
case InstName.Sysl:
return true;
}
return false;
}
public static bool IsPrivileged(this InstName name)
{
switch (name)
{
case InstName.Dcps1:
case InstName.Dcps2:
case InstName.Dcps3:
case InstName.Drps:
case InstName.Eret:
case InstName.Ereta:
case InstName.Hvc:
case InstName.MsrImm:
case InstName.Smc:
return true;
}
return false;
}
public static bool IsPartialRegisterUpdateMemory(this InstName name)
{
switch (name)
{
case InstName.Ld1AdvsimdSnglAsNoPostIndex:
case InstName.Ld1AdvsimdSnglAsPostIndex:
case InstName.Ld2AdvsimdSnglAsNoPostIndex:
case InstName.Ld2AdvsimdSnglAsPostIndex:
case InstName.Ld3AdvsimdSnglAsNoPostIndex:
case InstName.Ld3AdvsimdSnglAsPostIndex:
case InstName.Ld4AdvsimdSnglAsNoPostIndex:
case InstName.Ld4AdvsimdSnglAsPostIndex:
return true;
}
return false;
}
public static bool IsPrefetchMemory(this InstName name)
{
switch (name)
{
case InstName.PrfmImm:
case InstName.PrfmLit:
case InstName.PrfmReg:
case InstName.Prfum:
return true;
}
return false;
public bool IsPrefetchMemory => name is
InstName.PrfmImm or InstName.PrfmLit or InstName.PrfmReg or InstName.Prfum;
}
}
}

4
src/Ryujinx.Cpu/LightningJit/Arm64/RegisterUtils.cs
View file

@ -247,7 +247,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64
}
}
if (!flags.HasFlag(InstFlags.ReadRt) || name.IsPartialRegisterUpdateMemory())
if (!flags.HasFlag(InstFlags.ReadRt) || name.IsPartialRegisterUpdateMemory)
{
if (flags.HasFlag(InstFlags.Rt))
{
@ -281,7 +281,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64
gprMask |= MaskFromIndex(ExtractRd(flags, encoding));
}
if (!flags.HasFlag(InstFlags.ReadRt) || name.IsPartialRegisterUpdateMemory())
if (!flags.HasFlag(InstFlags.ReadRt) || name.IsPartialRegisterUpdateMemory)
{
if (flags.HasFlag(InstFlags.Rt))
{

4
src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/Compiler.cs
View file

@ -364,7 +364,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
{
InstEmitMemory.RewriteSysInstruction(memoryManager.AddressSpaceBits, memoryManager.Type, writer, regAlloc, encoding);
}
else if (instInfo.Name.IsSystem())
else if (instInfo.Name.IsSystem)
{
bool needsContextStoreLoad = InstEmitSystem.NeedsContextStoreLoad(instInfo.Name);
@ -405,7 +405,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
lastInstructionEncoding = RegisterUtils.RemapRegisters(regAlloc, lastInstructionFlags, lastInstructionEncoding);
if (lastInstructionName.IsCall())
if (lastInstructionName.IsCall)
{
context.StoreToContextBeforeCall(blockIndex, pc + 4UL);

12
src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/Decoder.cs
View file

@ -257,7 +257,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
(name, flags, AddressForm addressForm) = InstTable.GetInstNameAndFlags(encoding, cpuPreset.Version, cpuPreset.Features);
if (name.IsPrivileged() || (name == InstName.Sys && IsPrivilegedSys(encoding)))
if (name.IsPrivileged || (name == InstName.Sys && IsPrivilegedSys(encoding)))
{
name = InstName.UdfPermUndef;
flags = InstFlags.None;
@ -267,7 +267,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
(uint instGprReadMask, uint instFpSimdReadMask) = RegisterUtils.PopulateReadMasks(name, flags, encoding);
(uint instGprWriteMask, uint instFpSimdWriteMask) = RegisterUtils.PopulateWriteMasks(name, flags, encoding);
if (name.IsCall())
if (name.IsCall)
{
instGprWriteMask |= 1u << RegisterUtils.LrIndex;
}
@ -310,12 +310,12 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
fpSimdUseMask |= instFpSimdReadMask | instFpSimdWriteMask;
pStateUseMask |= instPStateReadMask | instPStateWriteMask;
if (name.IsSystemOrCall() && !hasHostCall)
if (name.IsSystemOrCall && !hasHostCall)
{
hasHostCall = name.IsCall() || InstEmitSystem.NeedsCall(encoding);
hasHostCall = name.IsCall || InstEmitSystem.NeedsCall(encoding);
}
isControlFlow = name.IsControlFlowOrException();
isControlFlow = name.IsControlFlowOrException;
RegisterUse registerUse = new(
instGprReadMask,
@ -339,7 +339,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
useMask = new(gprUseMask, fpSimdUseMask, pStateUseMask);
return new(startAddress, address, insts, !isTruncated && !name.IsException(), isTruncated, isLoopEnd);
return new(startAddress, address, insts, !isTruncated && !name.IsException, isTruncated, isLoopEnd);
}
private static bool IsPrivilegedSys(uint encoding)

2
src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/InstEmitMemory.cs
View file

@ -55,7 +55,7 @@ namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64
ulong pc,
uint encoding)
{
if (name.IsPrefetchMemory() && mmType == MemoryManagerType.HostTrackedUnsafe)
if (name.IsPrefetchMemory && mmType == MemoryManagerType.HostTrackedUnsafe)
{
// Prefetch to invalid addresses do not cause faults, so for memory manager
// types where we need to access the page table before doing the prefetch,