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Structural and Memory Safety Improvements, Analyzer Cleanup (ryubing/ryujinx!47)

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See merge request ryubing/ryujinx!47
This commit is contained in:
MrKev 2025-06-11 17:58:27 -05:00 • committed by LotP
parent d03ae9c164
commit ea027d65a7
309 changed files with 1018 additions and 1247 deletions
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46
src/ARMeilleure/Instructions/InstEmitSimdMemory.cs
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@ -40,34 +40,36 @@ namespace ARMeilleure.Instructions
long offset = 0;
#pragma warning disable IDE0055 // Disable formatting
for (int rep = 0; rep < op.Reps; rep++)
for (int elem = 0; elem < op.Elems; elem++)
for (int sElem = 0; sElem < op.SElems; sElem++)
for (int rep = 0; rep < op.Reps; rep++)
{
int rtt = (op.Rt + rep + sElem) & 0x1f;
Operand tt = GetVec(rtt);
Operand address = context.Add(n, Const(offset));
if (isLoad)
for (int elem = 0; elem < op.Elems; elem++)
{
EmitLoadSimd(context, address, tt, rtt, elem, op.Size);
if (op.RegisterSize == RegisterSize.Simd64 && elem == op.Elems - 1)
for (int sElem = 0; sElem < op.SElems; sElem++)
{
context.Copy(tt, context.VectorZeroUpper64(tt));
int rtt = (op.Rt + rep + sElem) & 0x1f;
Operand tt = GetVec(rtt);
Operand address = context.Add(n, Const(offset));
if (isLoad)
{
EmitLoadSimd(context, address, tt, rtt, elem, op.Size);
if (op.RegisterSize == RegisterSize.Simd64 && elem == op.Elems - 1)
{
context.Copy(tt, context.VectorZeroUpper64(tt));
}
}
else
{
EmitStoreSimd(context, address, rtt, elem, op.Size);
}
offset += 1 << op.Size;
}
}
else
{
EmitStoreSimd(context, address, rtt, elem, op.Size);
}
offset += 1 << op.Size;
}
#pragma warning restore IDE0055
if (op.WBack)
{