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Rename ARegisters to AThreadState

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This commit is contained in:
gdkchan 2018-02-18 16:28:07 -03:00
parent 5a0396efaf
commit f35d286c8d
25 changed files with 303 additions and 301 deletions
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6
Ryujinx/Cpu/AThread.cs
View file

@ -7,7 +7,7 @@ namespace ChocolArm64
{
public class AThread
{
public ARegisters Registers { get; private set; }
public AThreadState ThreadState { get; private set; }
public AMemory Memory { get; private set; }
public long EntryPoint { get; private set; }
@ -20,7 +20,7 @@ namespace ChocolArm64
public event EventHandler WorkFinished;
public int ThreadId => Registers.ThreadId;
public int ThreadId => ThreadState.ThreadId;
public bool IsAlive => Work.IsAlive;
@ -34,7 +34,7 @@ namespace ChocolArm64
this.Priority = Priority;
this.EntryPoint = EntryPoint;
Registers = new ARegisters();
ThreadState = new AThreadState();
Translator = new ATranslator(this);
ExecuteLock = new object();
}

16
Ryujinx/Cpu/ATranslatedSub.cs
View file

@ -9,7 +9,7 @@ namespace ChocolArm64
{
class ATranslatedSub
{
private delegate long AA64Subroutine(ARegisters Register, AMemory Memory);
private delegate long AA64Subroutine(AThreadState Register, AMemory Memory);
private AA64Subroutine ExecDelegate;
@ -17,8 +17,8 @@ namespace ChocolArm64
public static Type[] FixedArgTypes { get; private set; }
public static int RegistersArgIdx { get; private set; }
public static int MemoryArgIdx { get; private set; }
public static int StateArgIdx { get; private set; }
public static int MemoryArgIdx { get; private set; }
public DynamicMethod Method { get; private set; }
@ -58,9 +58,9 @@ namespace ChocolArm64
FixedArgTypes[Index] = ParamType;
if (ParamType == typeof(ARegisters))
if (ParamType == typeof(AThreadState))
{
RegistersArgIdx = Index;
StateArgIdx = Index;
}
else if (ParamType == typeof(AMemory))
{
@ -69,7 +69,7 @@ namespace ChocolArm64
}
}
public long Execute(ARegisters Registers, AMemory Memory)
public long Execute(AThreadState ThreadState, AMemory Memory)
{
if (!HasDelegate)
{
@ -83,7 +83,7 @@ namespace ChocolArm64
foreach (ARegister Reg in Params)
{
Generator.EmitLdarg(RegistersArgIdx);
Generator.EmitLdarg(StateArgIdx);
Generator.Emit(OpCodes.Ldfld, Reg.GetField());
}
@ -96,7 +96,7 @@ namespace ChocolArm64
HasDelegate = true;
}
return ExecDelegate(Registers, Memory);
return ExecDelegate(ThreadState, Memory);
}
public void MarkForReJit() => NeedsReJit = true;

6
Ryujinx/Cpu/ATranslator.cs
View file

@ -31,14 +31,14 @@ namespace ChocolArm64
{
if (CachedSubs.TryGetValue(Position, out ATranslatedSub Sub) && !Sub.NeedsReJit)
{
Position = Sub.Execute(Thread.Registers, Thread.Memory);
Position = Sub.Execute(Thread.ThreadState, Thread.Memory);
}
else
{
Position = TranslateSubroutine(Position).Execute(Thread.Registers, Thread.Memory);
Position = TranslateSubroutine(Position).Execute(Thread.ThreadState, Thread.Memory);
}
}
while (Position != 0 && KeepRunning);
while (Position != 0 && KeepRunning);
}
public bool TryGetCachedSub(AOpCode OpCode, out ATranslatedSub Sub)

2
Ryujinx/Cpu/Decoder/AOpCodeCcmp.cs
View file

@ -25,7 +25,7 @@ namespace ChocolArm64.Decoder
Cond = (ACond)((OpCode >> 12) & 0xf);
RmImm = (OpCode >> 16) & 0x1f;
Rd = ARegisters.ZRIndex;
Rd = AThreadState.ZRIndex;
}
}
}

5
Ryujinx/Cpu/Instruction/AInstEmitAlu.cs
View file

@ -343,8 +343,11 @@ namespace ChocolArm64.Instruction
private static void EmitZeroCVFlags(AILEmitterCtx Context)
{
Context.EmitLdc_I4(0);
Context.EmitLdc_I4(0);
Context.EmitStflg((int)APState.VBit);
Context.EmitLdc_I4(0);
Context.EmitStflg((int)APState.CBit);
}
}

14
Ryujinx/Cpu/Instruction/AInstEmitException.cs
View file

@ -11,12 +11,12 @@ namespace ChocolArm64.Instruction
public static void Brk(AILEmitterCtx Context)
{
EmitExceptionCall(Context, nameof(ARegisters.OnBreak));
EmitExceptionCall(Context, nameof(AThreadState.OnBreak));
}
public static void Svc(AILEmitterCtx Context)
{
EmitExceptionCall(Context, nameof(ARegisters.OnSvcCall));
EmitExceptionCall(Context, nameof(AThreadState.OnSvcCall));
}
private static void EmitExceptionCall(AILEmitterCtx Context, string MthdName)
@ -25,11 +25,11 @@ namespace ChocolArm64.Instruction
Context.EmitStoreState();
Context.EmitLdarg(ATranslatedSub.RegistersArgIdx);
Context.EmitLdarg(ATranslatedSub.StateArgIdx);
Context.EmitLdc_I4(Op.Id);
MethodInfo MthdInfo = typeof(ARegisters).GetMethod(MthdName, Binding);
MethodInfo MthdInfo = typeof(AThreadState).GetMethod(MthdName, Binding);
Context.EmitCall(MthdInfo);
@ -45,14 +45,14 @@ namespace ChocolArm64.Instruction
Context.EmitStoreState();
Context.EmitLdarg(ATranslatedSub.RegistersArgIdx);
Context.EmitLdarg(ATranslatedSub.StateArgIdx);
Context.EmitLdc_I8(Op.Position);
Context.EmitLdc_I4(Op.RawOpCode);
string MthdName = nameof(ARegisters.OnUndefined);
string MthdName = nameof(AThreadState.OnUndefined);
MethodInfo MthdInfo = typeof(ARegisters).GetMethod(MthdName, Binding);
MethodInfo MthdInfo = typeof(AThreadState).GetMethod(MthdName, Binding);
Context.EmitCall(MthdInfo);

6
Ryujinx/Cpu/Instruction/AInstEmitFlow.cs
View file

@ -26,7 +26,7 @@ namespace ChocolArm64.Instruction
AOpCodeBImmAl Op = (AOpCodeBImmAl)Context.CurrOp;
Context.EmitLdc_I(Op.Position + 4);
Context.EmitStint(ARegisters.LRIndex);
Context.EmitStint(AThreadState.LRIndex);
Context.EmitStoreState();
if (Context.TryOptEmitSubroutineCall())
@ -66,7 +66,7 @@ namespace ChocolArm64.Instruction
AOpCodeBReg Op = (AOpCodeBReg)Context.CurrOp;
Context.EmitLdc_I(Op.Position + 4);
Context.EmitStint(ARegisters.LRIndex);
Context.EmitStint(AThreadState.LRIndex);
Context.EmitStoreState();
Context.EmitLdintzr(Op.Rn);
@ -99,7 +99,7 @@ namespace ChocolArm64.Instruction
public static void Ret(AILEmitterCtx Context)
{
Context.EmitStoreState();
Context.EmitLdint(ARegisters.LRIndex);
Context.EmitLdint(AThreadState.LRIndex);
Context.Emit(OpCodes.Ret);
}

2
Ryujinx/Cpu/Instruction/AInstEmitMemoryEx.cs
View file

@ -159,7 +159,7 @@ namespace ChocolArm64.Instruction
private static void EmitMemoryCall(AILEmitterCtx Context, string Name, int Rn = -1)
{
Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
Context.EmitLdarg(ATranslatedSub.RegistersArgIdx);
Context.EmitLdarg(ATranslatedSub.StateArgIdx);
if (Rn != -1)
{

2
Ryujinx/Cpu/Instruction/AInstEmitSimdMemory.cs
View file

@ -167,7 +167,7 @@ namespace ChocolArm64.Instruction
Context.EmitLdint(Op.Rn);
if (Op.Rm != ARegisters.ZRIndex)
if (Op.Rm != AThreadState.ZRIndex)
{
Context.EmitLdint(Op.Rm);
}

34
Ryujinx/Cpu/Instruction/AInstEmitSystem.cs
View file

@ -13,26 +13,26 @@ namespace ChocolArm64.Instruction
{
AOpCodeSystem Op = (AOpCodeSystem)Context.CurrOp;
Context.EmitLdarg(ATranslatedSub.RegistersArgIdx);
Context.EmitLdarg(ATranslatedSub.StateArgIdx);
string PropName;
switch (GetPackedId(Op))
{
case 0b11_011_0000_0000_001: PropName = nameof(ARegisters.CtrEl0); break;
case 0b11_011_0000_0000_111: PropName = nameof(ARegisters.DczidEl0); break;
case 0b11_011_0100_0100_000: PropName = nameof(ARegisters.Fpcr); break;
case 0b11_011_0100_0100_001: PropName = nameof(ARegisters.Fpsr); break;
case 0b11_011_1101_0000_010: PropName = nameof(ARegisters.TpidrEl0); break;
case 0b11_011_1101_0000_011: PropName = nameof(ARegisters.Tpidr); break;
case 0b11_011_1110_0000_001: PropName = nameof(ARegisters.CntpctEl0); break;
case 0b11_011_0000_0000_001: PropName = nameof(AThreadState.CtrEl0); break;
case 0b11_011_0000_0000_111: PropName = nameof(AThreadState.DczidEl0); break;
case 0b11_011_0100_0100_000: PropName = nameof(AThreadState.Fpcr); break;
case 0b11_011_0100_0100_001: PropName = nameof(AThreadState.Fpsr); break;
case 0b11_011_1101_0000_010: PropName = nameof(AThreadState.TpidrEl0); break;
case 0b11_011_1101_0000_011: PropName = nameof(AThreadState.Tpidr); break;
case 0b11_011_1110_0000_001: PropName = nameof(AThreadState.CntpctEl0); break;
default: throw new NotImplementedException($"Unknown MRS at {Op.Position:x16}");
}
Context.EmitCallPropGet(typeof(ARegisters), PropName);
Context.EmitCallPropGet(typeof(AThreadState), PropName);
PropertyInfo PropInfo = typeof(ARegisters).GetProperty(PropName);
PropertyInfo PropInfo = typeof(AThreadState).GetProperty(PropName);
if (PropInfo.PropertyType != typeof(long) &&
PropInfo.PropertyType != typeof(ulong))
@ -47,21 +47,21 @@ namespace ChocolArm64.Instruction
{
AOpCodeSystem Op = (AOpCodeSystem)Context.CurrOp;
Context.EmitLdarg(ATranslatedSub.RegistersArgIdx);
Context.EmitLdarg(ATranslatedSub.StateArgIdx);
Context.EmitLdintzr(Op.Rt);
string PropName;
switch (GetPackedId(Op))
{
case 0b11_011_0100_0100_000: PropName = nameof(ARegisters.Fpcr); break;
case 0b11_011_0100_0100_001: PropName = nameof(ARegisters.Fpsr); break;
case 0b11_011_1101_0000_010: PropName = nameof(ARegisters.TpidrEl0); break;
case 0b11_011_0100_0100_000: PropName = nameof(AThreadState.Fpcr); break;
case 0b11_011_0100_0100_001: PropName = nameof(AThreadState.Fpsr); break;
case 0b11_011_1101_0000_010: PropName = nameof(AThreadState.TpidrEl0); break;
default: throw new NotImplementedException($"Unknown MSR at {Op.Position:x16}");
}
PropertyInfo PropInfo = typeof(ARegisters).GetProperty(PropName);
PropertyInfo PropInfo = typeof(AThreadState).GetProperty(PropName);
if (PropInfo.PropertyType != typeof(long) &&
PropInfo.PropertyType != typeof(ulong))
@ -69,7 +69,7 @@ namespace ChocolArm64.Instruction
Context.Emit(OpCodes.Conv_U4);
}
Context.EmitCallPropSet(typeof(ARegisters), PropName);
Context.EmitCallPropSet(typeof(AThreadState), PropName);
}
public static void Nop(AILEmitterCtx Context)
@ -89,7 +89,7 @@ namespace ChocolArm64.Instruction
case 0b11_011_0111_0100_001:
{
//DC ZVA
for (int Offs = 0; Offs < (4 << ARegisters.DczSizeLog2); Offs += 8)
for (int Offs = 0; Offs < (4 << AThreadState.DczSizeLog2); Offs += 8)
{
Context.EmitLdarg(ATranslatedSub.MemoryArgIdx);
Context.EmitLdint(Op.Rt);

18
Ryujinx/Cpu/Memory/AMemory.cs
View file

@ -8,7 +8,7 @@ namespace ChocolArm64.Memory
{
public unsafe class AMemory
{
private const long ErgMask = (4 << ARegisters.ErgSizeLog2) - 1;
private const long ErgMask = (4 << AThreadState.ErgSizeLog2) - 1;
public AMemoryMgr Manager { get; private set; }
@ -65,13 +65,13 @@ namespace ChocolArm64.Memory
}
}
public void SetExclusive(ARegisters Registers, long Position)
public void SetExclusive(AThreadState ThreadState, long Position)
{
Position &= ~ErgMask;
lock (Monitors)
{
if (Monitors.TryGetValue(Registers.ThreadId, out ExMonitor Monitor))
if (Monitors.TryGetValue(ThreadState.ThreadId, out ExMonitor Monitor))
{
ExAddrs.Remove(Monitor.Position);
}
@ -80,20 +80,20 @@ namespace ChocolArm64.Memory
Monitor = new ExMonitor(Position, ExState);
if (!Monitors.TryAdd(Registers.ThreadId, Monitor))
if (!Monitors.TryAdd(ThreadState.ThreadId, Monitor))
{
Monitors[Registers.ThreadId] = Monitor;
Monitors[ThreadState.ThreadId] = Monitor;
}
}
}
public bool TestExclusive(ARegisters Registers, long Position)
public bool TestExclusive(AThreadState ThreadState, long Position)
{
Position &= ~ErgMask;
lock (Monitors)
{
if (!Monitors.TryGetValue(Registers.ThreadId, out ExMonitor Monitor))
if (!Monitors.TryGetValue(ThreadState.ThreadId, out ExMonitor Monitor))
{
return false;
}
@ -102,11 +102,11 @@ namespace ChocolArm64.Memory
}
}
public void ClearExclusive(ARegisters Registers)
public void ClearExclusive(AThreadState ThreadState)
{
lock (Monitors)
{
if (Monitors.TryGetValue(Registers.ThreadId, out ExMonitor Monitor))
if (Monitors.TryGetValue(ThreadState.ThreadId, out ExMonitor Monitor))
{
Monitor.Reset();
ExAddrs.Remove(Monitor.Position);

138
Ryujinx/Cpu/State/ARegister.cs
View file

@ -43,10 +43,10 @@ namespace ChocolArm64.State
{
switch ((APState)Index)
{
case APState.VBit: return GetField(nameof(ARegisters.Overflow));
case APState.CBit: return GetField(nameof(ARegisters.Carry));
case APState.ZBit: return GetField(nameof(ARegisters.Zero));
case APState.NBit: return GetField(nameof(ARegisters.Negative));
case APState.VBit: return GetField(nameof(AThreadState.Overflow));
case APState.CBit: return GetField(nameof(AThreadState.Carry));
case APState.ZBit: return GetField(nameof(AThreadState.Zero));
case APState.NBit: return GetField(nameof(AThreadState.Negative));
}
throw new InvalidOperationException();
@ -56,38 +56,38 @@ namespace ChocolArm64.State
{
switch (Index)
{
case 0: return GetField(nameof(ARegisters.X0));
case 1: return GetField(nameof(ARegisters.X1));
case 2: return GetField(nameof(ARegisters.X2));
case 3: return GetField(nameof(ARegisters.X3));
case 4: return GetField(nameof(ARegisters.X4));
case 5: return GetField(nameof(ARegisters.X5));
case 6: return GetField(nameof(ARegisters.X6));
case 7: return GetField(nameof(ARegisters.X7));
case 8: return GetField(nameof(ARegisters.X8));
case 9: return GetField(nameof(ARegisters.X9));
case 10: return GetField(nameof(ARegisters.X10));
case 11: return GetField(nameof(ARegisters.X11));
case 12: return GetField(nameof(ARegisters.X12));
case 13: return GetField(nameof(ARegisters.X13));
case 14: return GetField(nameof(ARegisters.X14));
case 15: return GetField(nameof(ARegisters.X15));
case 16: return GetField(nameof(ARegisters.X16));
case 17: return GetField(nameof(ARegisters.X17));
case 18: return GetField(nameof(ARegisters.X18));
case 19: return GetField(nameof(ARegisters.X19));
case 20: return GetField(nameof(ARegisters.X20));
case 21: return GetField(nameof(ARegisters.X21));
case 22: return GetField(nameof(ARegisters.X22));
case 23: return GetField(nameof(ARegisters.X23));
case 24: return GetField(nameof(ARegisters.X24));
case 25: return GetField(nameof(ARegisters.X25));
case 26: return GetField(nameof(ARegisters.X26));
case 27: return GetField(nameof(ARegisters.X27));
case 28: return GetField(nameof(ARegisters.X28));
case 29: return GetField(nameof(ARegisters.X29));
case 30: return GetField(nameof(ARegisters.X30));
case 31: return GetField(nameof(ARegisters.X31));
case 0: return GetField(nameof(AThreadState.X0));
case 1: return GetField(nameof(AThreadState.X1));
case 2: return GetField(nameof(AThreadState.X2));
case 3: return GetField(nameof(AThreadState.X3));
case 4: return GetField(nameof(AThreadState.X4));
case 5: return GetField(nameof(AThreadState.X5));
case 6: return GetField(nameof(AThreadState.X6));
case 7: return GetField(nameof(AThreadState.X7));
case 8: return GetField(nameof(AThreadState.X8));
case 9: return GetField(nameof(AThreadState.X9));
case 10: return GetField(nameof(AThreadState.X10));
case 11: return GetField(nameof(AThreadState.X11));
case 12: return GetField(nameof(AThreadState.X12));
case 13: return GetField(nameof(AThreadState.X13));
case 14: return GetField(nameof(AThreadState.X14));
case 15: return GetField(nameof(AThreadState.X15));
case 16: return GetField(nameof(AThreadState.X16));
case 17: return GetField(nameof(AThreadState.X17));
case 18: return GetField(nameof(AThreadState.X18));
case 19: return GetField(nameof(AThreadState.X19));
case 20: return GetField(nameof(AThreadState.X20));
case 21: return GetField(nameof(AThreadState.X21));
case 22: return GetField(nameof(AThreadState.X22));
case 23: return GetField(nameof(AThreadState.X23));
case 24: return GetField(nameof(AThreadState.X24));
case 25: return GetField(nameof(AThreadState.X25));
case 26: return GetField(nameof(AThreadState.X26));
case 27: return GetField(nameof(AThreadState.X27));
case 28: return GetField(nameof(AThreadState.X28));
case 29: return GetField(nameof(AThreadState.X29));
case 30: return GetField(nameof(AThreadState.X30));
case 31: return GetField(nameof(AThreadState.X31));
}
throw new InvalidOperationException();
@ -97,38 +97,38 @@ namespace ChocolArm64.State
{
switch (Index)
{
case 0: return GetField(nameof(ARegisters.V0));
case 1: return GetField(nameof(ARegisters.V1));
case 2: return GetField(nameof(ARegisters.V2));
case 3: return GetField(nameof(ARegisters.V3));
case 4: return GetField(nameof(ARegisters.V4));
case 5: return GetField(nameof(ARegisters.V5));
case 6: return GetField(nameof(ARegisters.V6));
case 7: return GetField(nameof(ARegisters.V7));
case 8: return GetField(nameof(ARegisters.V8));
case 9: return GetField(nameof(ARegisters.V9));
case 10: return GetField(nameof(ARegisters.V10));
case 11: return GetField(nameof(ARegisters.V11));
case 12: return GetField(nameof(ARegisters.V12));
case 13: return GetField(nameof(ARegisters.V13));
case 14: return GetField(nameof(ARegisters.V14));
case 15: return GetField(nameof(ARegisters.V15));
case 16: return GetField(nameof(ARegisters.V16));
case 17: return GetField(nameof(ARegisters.V17));
case 18: return GetField(nameof(ARegisters.V18));
case 19: return GetField(nameof(ARegisters.V19));
case 20: return GetField(nameof(ARegisters.V20));
case 21: return GetField(nameof(ARegisters.V21));
case 22: return GetField(nameof(ARegisters.V22));
case 23: return GetField(nameof(ARegisters.V23));
case 24: return GetField(nameof(ARegisters.V24));
case 25: return GetField(nameof(ARegisters.V25));
case 26: return GetField(nameof(ARegisters.V26));
case 27: return GetField(nameof(ARegisters.V27));
case 28: return GetField(nameof(ARegisters.V28));
case 29: return GetField(nameof(ARegisters.V29));
case 30: return GetField(nameof(ARegisters.V30));
case 31: return GetField(nameof(ARegisters.V31));
case 0: return GetField(nameof(AThreadState.V0));
case 1: return GetField(nameof(AThreadState.V1));
case 2: return GetField(nameof(AThreadState.V2));
case 3: return GetField(nameof(AThreadState.V3));
case 4: return GetField(nameof(AThreadState.V4));
case 5: return GetField(nameof(AThreadState.V5));
case 6: return GetField(nameof(AThreadState.V6));
case 7: return GetField(nameof(AThreadState.V7));
case 8: return GetField(nameof(AThreadState.V8));
case 9: return GetField(nameof(AThreadState.V9));
case 10: return GetField(nameof(AThreadState.V10));
case 11: return GetField(nameof(AThreadState.V11));
case 12: return GetField(nameof(AThreadState.V12));
case 13: return GetField(nameof(AThreadState.V13));
case 14: return GetField(nameof(AThreadState.V14));
case 15: return GetField(nameof(AThreadState.V15));
case 16: return GetField(nameof(AThreadState.V16));
case 17: return GetField(nameof(AThreadState.V17));
case 18: return GetField(nameof(AThreadState.V18));
case 19: return GetField(nameof(AThreadState.V19));
case 20: return GetField(nameof(AThreadState.V20));
case 21: return GetField(nameof(AThreadState.V21));
case 22: return GetField(nameof(AThreadState.V22));
case 23: return GetField(nameof(AThreadState.V23));
case 24: return GetField(nameof(AThreadState.V24));
case 25: return GetField(nameof(AThreadState.V25));
case 26: return GetField(nameof(AThreadState.V26));
case 27: return GetField(nameof(AThreadState.V27));
case 28: return GetField(nameof(AThreadState.V28));
case 29: return GetField(nameof(AThreadState.V29));
case 30: return GetField(nameof(AThreadState.V30));
case 31: return GetField(nameof(AThreadState.V31));
}
throw new InvalidOperationException();
@ -136,7 +136,7 @@ namespace ChocolArm64.State
private FieldInfo GetField(string Name)
{
return typeof(ARegisters).GetField(Name);
return typeof(AThreadState).GetField(Name);
}
}
}

2
Ryujinx/Cpu/State/ARegisters.cs → Ryujinx/Cpu/State/AThreadState.cs
View file

@ -2,7 +2,7 @@ using System;
namespace ChocolArm64.State
{
public class ARegisters
public class AThreadState
{
internal const int LRIndex = 30;
internal const int ZRIndex = 31;

4
Ryujinx/Cpu/Translation/AILEmitterCtx.cs
View file

@ -309,7 +309,7 @@ namespace ChocolArm64.Translation
public void EmitLdintzr(int Index)
{
if (Index != ARegisters.ZRIndex)
if (Index != AThreadState.ZRIndex)
{
EmitLdint(Index);
}
@ -321,7 +321,7 @@ namespace ChocolArm64.Translation
public void EmitStintzr(int Index)
{
if (Index != ARegisters.ZRIndex)
if (Index != AThreadState.ZRIndex)
{
EmitStint(Index);
}

2
Ryujinx/Cpu/Translation/AILOpCodeLoad.cs
View file

@ -53,7 +53,7 @@ namespace ChocolArm64.Translation
{
ARegister Reg = AILEmitter.GetRegFromBit(Bit, BaseType);
Context.Generator.EmitLdarg(ATranslatedSub.RegistersArgIdx);
Context.Generator.EmitLdarg(ATranslatedSub.StateArgIdx);
Context.Generator.Emit(OpCodes.Ldfld, Reg.GetField());
Context.Generator.EmitStloc(Context.GetLocalIndex(Reg));

2
Ryujinx/Cpu/Translation/AILOpCodeStore.cs
View file

@ -53,7 +53,7 @@ namespace ChocolArm64.Translation
{
ARegister Reg = AILEmitter.GetRegFromBit(Bit, BaseType);
Context.Generator.EmitLdarg(ATranslatedSub.RegistersArgIdx);
Context.Generator.EmitLdarg(ATranslatedSub.StateArgIdx);
Context.Generator.EmitLdloc(Context.GetLocalIndex(Reg));
Context.Generator.Emit(OpCodes.Stfld, Reg.GetField());