mirror of
https://git.ryujinx.app/ryubing/ryujinx.git
synced 2025-07-29 07:47:11 +02:00
[ARMeilleure] Address dotnet-format issues (#5357)
* dotnet format style --severity info Some changes were manually reverted. * dotnet format analyzers --serverity info Some changes have been minimally adapted. * Restore a few unused methods and variables * Silence dotnet format IDE0060 warnings * Silence dotnet format IDE0052 warnings * Address or silence dotnet format IDE1006 warnings * Address or silence dotnet format CA2208 warnings * Address dotnet format CA1822 warnings * Address or silence dotnet format CA1069 warnings * Silence CA1806 and CA1834 issues * Address dotnet format CA1401 warnings * Fix new dotnet-format issues after rebase * Address review comments * Address dotnet format CA2208 warnings properly * Fix formatting for switch expressions * Address most dotnet format whitespace warnings * Apply dotnet format whitespace formatting A few of them have been manually reverted and the corresponding warning was silenced * Add previously silenced warnings back I have no clue how these disappeared * Revert formatting changes for OpCodeTable.cs * Enable formatting for a few cases again * Format if-blocks correctly * Enable formatting for a few more cases again * Fix inline comment alignment * Run dotnet format after rebase and remove unused usings - analyzers - style - whitespace * Disable 'prefer switch expression' rule * Add comments to disabled warnings * Remove a few unused parameters * Adjust namespaces * Simplify properties and array initialization, Use const when possible, Remove trailing commas * Start working on disabled warnings * Fix and silence a few dotnet-format warnings again * Address IDE0251 warnings * Address a few disabled IDE0060 warnings * Silence IDE0060 in .editorconfig * Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas" This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e. * dotnet format whitespace after rebase * First dotnet format pass * Remove unnecessary formatting exclusion * Add unsafe dotnet format changes * Change visibility of JitSupportDarwin to internal
This commit is contained in:
TSRBerry
GitHub
parent
2de78a2d55
commit
ff53dcf560
300 changed files with 3515 additions and 3120 deletions
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@ -5,10 +5,10 @@ namespace ARMeilleure.Decoders
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{
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class Block
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{
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public ulong Address { get; set; }
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public ulong Address { get; set; }
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public ulong EndAddress { get; set; }
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public Block Next { get; set; }
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public Block Next { get; set; }
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public Block Branch { get; set; }
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public bool Exit { get; set; }
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@ -43,14 +43,14 @@ namespace ARMeilleure.Decoders
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rightBlock.EndAddress = EndAddress;
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rightBlock.Next = Next;
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rightBlock.Next = Next;
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rightBlock.Branch = Branch;
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rightBlock.OpCodes.AddRange(OpCodes.GetRange(splitIndex, splitCount));
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EndAddress = rightBlock.Address;
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Next = rightBlock;
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Next = rightBlock;
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Branch = null;
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OpCodes.RemoveRange(splitIndex, splitCount);
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@ -58,9 +58,9 @@ namespace ARMeilleure.Decoders
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private static int BinarySearch(List<OpCode> opCodes, ulong address)
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{
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int left = 0;
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int left = 0;
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int middle = 0;
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int right = opCodes.Count - 1;
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int right = opCodes.Count - 1;
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while (left <= right)
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{
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@ -92,10 +92,10 @@ namespace ARMeilleure.Decoders
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{
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if (OpCodes.Count > 0)
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{
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return OpCodes[OpCodes.Count - 1];
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return OpCodes[^1];
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}
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return null;
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}
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}
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}
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}
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@ -2,22 +2,22 @@ namespace ARMeilleure.Decoders
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{
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enum Condition
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{
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Eq = 0,
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Ne = 1,
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Eq = 0,
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Ne = 1,
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GeUn = 2,
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LtUn = 3,
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Mi = 4,
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Pl = 5,
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Vs = 6,
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Vc = 7,
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Mi = 4,
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Pl = 5,
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Vs = 6,
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Vc = 7,
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GtUn = 8,
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LeUn = 9,
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Ge = 10,
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Lt = 11,
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Gt = 12,
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Le = 13,
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Al = 14,
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Nv = 15
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Ge = 10,
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Lt = 11,
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Gt = 12,
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Le = 13,
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Al = 14,
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Nv = 15,
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}
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static class ConditionExtensions
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@ -29,4 +29,4 @@ namespace ARMeilleure.Decoders
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return (Condition)((int)cond ^ 1);
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}
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}
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}
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}
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@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders
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{
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enum DataOp
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{
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Adr = 0,
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Adr = 0,
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Arithmetic = 1,
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Logical = 2,
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BitField = 3
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Logical = 2,
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BitField = 3,
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}
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}
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}
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@ -20,11 +20,11 @@ namespace ARMeilleure.Decoders
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public static Block[] Decode(IMemoryManager memory, ulong address, ExecutionMode mode, bool highCq, DecoderMode dMode)
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{
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List<Block> blocks = new List<Block>();
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List<Block> blocks = new();
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Queue<Block> workQueue = new Queue<Block>();
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Queue<Block> workQueue = new();
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Dictionary<ulong, Block> visited = new Dictionary<ulong, Block>();
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Dictionary<ulong, Block> visited = new();
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Debug.Assert(MaxInstsPerFunctionLowCq <= MaxInstsPerFunction);
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@ -163,7 +163,7 @@ namespace ARMeilleure.Decoders
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{
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index = 0;
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int left = 0;
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int left = 0;
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int right = blocks.Count - 1;
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while (left <= right)
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@ -196,9 +196,9 @@ namespace ARMeilleure.Decoders
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private static void FillBlock(
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IMemoryManager memory,
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ExecutionMode mode,
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Block block,
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ulong limitAddress)
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ExecutionMode mode,
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Block block,
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ulong limitAddress)
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{
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ulong address = block.Address;
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int itBlockSize = 0;
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@ -241,12 +241,12 @@ namespace ARMeilleure.Decoders
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private static bool IsUnconditionalBranch(OpCode opCode)
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{
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return opCode is OpCodeBImmAl ||
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opCode is OpCodeBReg || IsAarch32UnconditionalBranch(opCode);
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opCode is OpCodeBReg || IsAarch32UnconditionalBranch(opCode);
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}
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private static bool IsAarch32UnconditionalBranch(OpCode opCode)
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{
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if (!(opCode is OpCode32 op))
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if (opCode is not OpCode32 op)
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{
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return false;
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}
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@ -290,9 +290,9 @@ namespace ARMeilleure.Decoders
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if (opCode is IOpCode32Mem opMem)
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{
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rt = opMem.Rt;
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rn = opMem.Rn;
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wBack = opMem.WBack;
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rt = opMem.Rt;
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rn = opMem.Rn;
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wBack = opMem.WBack;
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isLoad = opMem.IsLoad;
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// For the dual load, we also need to take into account the
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@ -306,10 +306,10 @@ namespace ARMeilleure.Decoders
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{
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const int pcMask = 1 << RegisterAlias.Aarch32Pc;
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rt = (opMemMult.RegisterMask & pcMask) != 0 ? RegisterAlias.Aarch32Pc : 0;
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rn = opMemMult.Rn;
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wBack = opMemMult.PostOffset != 0;
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isLoad = opMemMult.IsLoad;
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rt = (opMemMult.RegisterMask & pcMask) != 0 ? RegisterAlias.Aarch32Pc : 0;
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rn = opMemMult.Rn;
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wBack = opMemMult.PostOffset != 0;
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isLoad = opMemMult.IsLoad;
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}
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else
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{
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@ -388,4 +388,4 @@ namespace ARMeilleure.Decoders
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}
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}
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}
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}
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}
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@ -10,7 +10,7 @@ namespace ARMeilleure.Decoders
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Imm8ToFP64Table = BuildImm8ToFP64Table();
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}
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public static readonly uint[] Imm8ToFP32Table;
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public static readonly uint[] Imm8ToFP32Table;
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public static readonly ulong[] Imm8ToFP64Table;
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private static uint[] BuildImm8ToFP32Table()
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@ -40,47 +40,47 @@ namespace ARMeilleure.Decoders
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// abcdefgh -> aBbbbbbc defgh000 00000000 00000000 (B = ~b)
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private static uint ExpandImm8ToFP32(uint imm)
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{
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uint MoveBit(uint bits, int from, int to)
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static uint MoveBit(uint bits, int from, int to)
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{
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return ((bits >> from) & 1U) << to;
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}
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return MoveBit(imm, 7, 31) | MoveBit(~imm, 6, 30) |
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MoveBit(imm, 6, 29) | MoveBit( imm, 6, 28) |
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MoveBit(imm, 6, 27) | MoveBit( imm, 6, 26) |
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MoveBit(imm, 6, 25) | MoveBit( imm, 5, 24) |
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MoveBit(imm, 4, 23) | MoveBit( imm, 3, 22) |
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MoveBit(imm, 2, 21) | MoveBit( imm, 1, 20) |
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MoveBit(imm, 6, 29) | MoveBit(imm, 6, 28) |
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MoveBit(imm, 6, 27) | MoveBit(imm, 6, 26) |
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MoveBit(imm, 6, 25) | MoveBit(imm, 5, 24) |
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MoveBit(imm, 4, 23) | MoveBit(imm, 3, 22) |
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MoveBit(imm, 2, 21) | MoveBit(imm, 1, 20) |
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MoveBit(imm, 0, 19);
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}
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// abcdefgh -> aBbbbbbb bbcdefgh 00000000 00000000 00000000 00000000 00000000 00000000 (B = ~b)
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private static ulong ExpandImm8ToFP64(ulong imm)
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{
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ulong MoveBit(ulong bits, int from, int to)
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static ulong MoveBit(ulong bits, int from, int to)
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{
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return ((bits >> from) & 1UL) << to;
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}
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return MoveBit(imm, 7, 63) | MoveBit(~imm, 6, 62) |
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MoveBit(imm, 6, 61) | MoveBit( imm, 6, 60) |
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MoveBit(imm, 6, 59) | MoveBit( imm, 6, 58) |
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MoveBit(imm, 6, 57) | MoveBit( imm, 6, 56) |
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MoveBit(imm, 6, 55) | MoveBit( imm, 6, 54) |
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MoveBit(imm, 5, 53) | MoveBit( imm, 4, 52) |
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MoveBit(imm, 3, 51) | MoveBit( imm, 2, 50) |
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MoveBit(imm, 1, 49) | MoveBit( imm, 0, 48);
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MoveBit(imm, 6, 61) | MoveBit(imm, 6, 60) |
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MoveBit(imm, 6, 59) | MoveBit(imm, 6, 58) |
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MoveBit(imm, 6, 57) | MoveBit(imm, 6, 56) |
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MoveBit(imm, 6, 55) | MoveBit(imm, 6, 54) |
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MoveBit(imm, 5, 53) | MoveBit(imm, 4, 52) |
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MoveBit(imm, 3, 51) | MoveBit(imm, 2, 50) |
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MoveBit(imm, 1, 49) | MoveBit(imm, 0, 48);
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}
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public struct BitMask
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{
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public long WMask;
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public long TMask;
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public int Pos;
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public int Shift;
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public int Pos;
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public int Shift;
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public bool IsUndefined;
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public static BitMask Invalid => new BitMask { IsUndefined = true };
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public static BitMask Invalid => new() { IsUndefined = true };
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}
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public static BitMask DecodeBitMask(int opCode, bool immediate)
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@ -88,7 +88,7 @@ namespace ARMeilleure.Decoders
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int immS = (opCode >> 10) & 0x3f;
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int immR = (opCode >> 16) & 0x3f;
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int n = (opCode >> 22) & 1;
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int n = (opCode >> 22) & 1;
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int sf = (opCode >> 31) & 1;
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int length = BitUtils.HighestBitSet((~immS & 0x3f) | (n << 6));
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@ -115,7 +115,7 @@ namespace ARMeilleure.Decoders
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if (r > 0)
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{
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wMask = BitUtils.RotateRight(wMask, r, size);
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wMask = BitUtils.RotateRight(wMask, r, size);
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wMask &= BitUtils.FillWithOnes(size);
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}
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@ -124,8 +124,8 @@ namespace ARMeilleure.Decoders
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WMask = BitUtils.Replicate(wMask, size),
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TMask = BitUtils.Replicate(tMask, size),
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Pos = immS,
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Shift = immR
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Pos = immS,
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Shift = immR,
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};
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}
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@ -164,4 +164,4 @@ namespace ARMeilleure.Decoders
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return false;
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}
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}
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}
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}
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@ -6,4 +6,4 @@
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SingleBlock,
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SingleInstruction,
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}
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}
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}
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@ -14,4 +14,4 @@ namespace ARMeilleure.Decoders
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OperandType GetOperandType();
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}
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}
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}
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@ -6,4 +6,4 @@ namespace ARMeilleure.Decoders
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uint GetPc();
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}
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}
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}
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@ -5,4 +5,4 @@ namespace ARMeilleure.Decoders
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int Rd { get; }
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int Rn { get; }
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}
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}
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}
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@ -6,4 +6,4 @@
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bool IsRotated { get; }
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}
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}
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}
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@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders
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{
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int Immediate { get; }
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}
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}
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}
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@ -7,4 +7,4 @@
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ShiftType ShiftType { get; }
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}
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}
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}
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@ -7,4 +7,4 @@
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ShiftType ShiftType { get; }
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}
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}
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}
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@ -1,4 +1,4 @@
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namespace ARMeilleure.Decoders
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{
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interface IOpCode32BImm : IOpCode32, IOpCodeBImm { }
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}
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}
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@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders
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{
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int Rm { get; }
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}
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}
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}
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@ -4,4 +4,4 @@
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{
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int Id { get; }
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}
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}
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}
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@ -4,4 +4,4 @@
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{
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bool? SetFlags { get; }
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}
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}
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}
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@ -13,4 +13,4 @@ namespace ARMeilleure.Decoders
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|
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int Immediate { get; }
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}
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}
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}
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|
|
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@ -12,4 +12,4 @@ namespace ARMeilleure.Decoders
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|
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int Offset { get; }
|
||||
}
|
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}
|
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}
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|
|
|
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|
|
@ -4,4 +4,4 @@
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{
|
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int Rm { get; }
|
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}
|
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}
|
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}
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|
|
|
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|
|
@ -5,4 +5,4 @@ namespace ARMeilleure.Decoders
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int Rm { get; }
|
||||
ShiftType ShiftType { get; }
|
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}
|
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}
|
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}
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|
|
|
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|
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@ -7,4 +7,4 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
DataOp DataOp { get; }
|
||||
}
|
||||
}
|
||||
}
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|
|
|
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|
|
@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders
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|||
{
|
||||
long Immediate { get; }
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
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@ -3,8 +3,8 @@ namespace ARMeilleure.Decoders
|
|||
interface IOpCodeAluRs : IOpCodeAlu
|
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{
|
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int Shift { get; }
|
||||
int Rm { get; }
|
||||
int Rm { get; }
|
||||
|
||||
ShiftType ShiftType { get; }
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
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|
|
@ -3,8 +3,8 @@ namespace ARMeilleure.Decoders
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interface IOpCodeAluRx : IOpCodeAlu
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{
|
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int Shift { get; }
|
||||
int Rm { get; }
|
||||
int Rm { get; }
|
||||
|
||||
IntType IntType { get; }
|
||||
}
|
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}
|
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}
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|
|
|
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|
|
@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders
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{
|
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long Immediate { get; }
|
||||
}
|
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}
|
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}
|
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|
|
|
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|
|
@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders
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{
|
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Condition Cond { get; }
|
||||
}
|
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}
|
||||
}
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|
|
|||
|
|
@ -2,10 +2,10 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
interface IOpCodeLit : IOpCode
|
||||
{
|
||||
int Rt { get; }
|
||||
int Rt { get; }
|
||||
long Immediate { get; }
|
||||
int Size { get; }
|
||||
bool Signed { get; }
|
||||
bool Prefetch { get; }
|
||||
int Size { get; }
|
||||
bool Signed { get; }
|
||||
bool Prefetch { get; }
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
int Size { get; }
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,15 +4,15 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
readonly struct InstDescriptor
|
||||
{
|
||||
public static InstDescriptor Undefined => new InstDescriptor(InstName.Und, InstEmit.Und);
|
||||
public static InstDescriptor Undefined => new(InstName.Und, InstEmit.Und);
|
||||
|
||||
public InstName Name { get; }
|
||||
public InstName Name { get; }
|
||||
public InstEmitter Emitter { get; }
|
||||
|
||||
public InstDescriptor(InstName name, InstEmitter emitter)
|
||||
{
|
||||
Name = name;
|
||||
Name = name;
|
||||
Emitter = emitter;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3,4 +3,4 @@ using ARMeilleure.Translation;
|
|||
namespace ARMeilleure.Decoders
|
||||
{
|
||||
delegate void InstEmitter(ArmEmitterContext context);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,13 +2,13 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
enum IntType
|
||||
{
|
||||
UInt8 = 0,
|
||||
UInt8 = 0,
|
||||
UInt16 = 1,
|
||||
UInt32 = 2,
|
||||
UInt64 = 3,
|
||||
Int8 = 4,
|
||||
Int16 = 5,
|
||||
Int32 = 6,
|
||||
Int64 = 7
|
||||
Int8 = 4,
|
||||
Int16 = 5,
|
||||
Int32 = 6,
|
||||
Int64 = 7,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -5,8 +5,8 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
class OpCode : IOpCode
|
||||
{
|
||||
public ulong Address { get; }
|
||||
public int RawOpCode { get; }
|
||||
public ulong Address { get; }
|
||||
public int RawOpCode { get; }
|
||||
|
||||
public int OpCodeSizeInBytes { get; protected set; } = 4;
|
||||
|
||||
|
|
@ -14,13 +14,13 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
public RegisterSize RegisterSize { get; protected set; }
|
||||
|
||||
public static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode(inst, address, opCode);
|
||||
public static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new(inst, address, opCode);
|
||||
|
||||
public OpCode(InstDescriptor inst, ulong address, int opCode)
|
||||
{
|
||||
Instruction = inst;
|
||||
Address = address;
|
||||
RawOpCode = opCode;
|
||||
Address = address;
|
||||
RawOpCode = opCode;
|
||||
|
||||
RegisterSize = RegisterSize.Int64;
|
||||
}
|
||||
|
|
@ -30,15 +30,14 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
public int GetBitsCount()
|
||||
{
|
||||
switch (RegisterSize)
|
||||
return RegisterSize switch
|
||||
{
|
||||
case RegisterSize.Int32: return 32;
|
||||
case RegisterSize.Int64: return 64;
|
||||
case RegisterSize.Simd64: return 64;
|
||||
case RegisterSize.Simd128: return 128;
|
||||
}
|
||||
|
||||
throw new InvalidOperationException();
|
||||
RegisterSize.Int32 => 32,
|
||||
RegisterSize.Int64 => 64,
|
||||
RegisterSize.Simd64 => 64,
|
||||
RegisterSize.Simd128 => 128,
|
||||
_ => throw new InvalidOperationException(),
|
||||
};
|
||||
}
|
||||
|
||||
public OperandType GetOperandType()
|
||||
|
|
@ -46,4 +45,4 @@ namespace ARMeilleure.Decoders
|
|||
return RegisterSize == RegisterSize.Int32 ? OperandType.I32 : OperandType.I64;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -31,4 +31,4 @@ namespace ARMeilleure.Decoders
|
|||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -17,4 +17,4 @@ namespace ARMeilleure.Decoders
|
|||
SetFlags = ((opCode >> 20) & 1) != 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -20,4 +20,4 @@ namespace ARMeilleure.Decoders
|
|||
IsRotated = shift != 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
class OpCode32AluRsImm : OpCode32Alu, IOpCode32AluRsImm
|
||||
{
|
||||
public int Rm { get; }
|
||||
public int Rm { get; }
|
||||
public int Immediate { get; }
|
||||
|
||||
public ShiftType ShiftType { get; }
|
||||
|
|
@ -11,10 +11,10 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
public OpCode32AluRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Rm = (opCode >> 0) & 0xf;
|
||||
Rm = (opCode >> 0) & 0xf;
|
||||
Immediate = (opCode >> 7) & 0x1f;
|
||||
|
||||
ShiftType = (ShiftType)((opCode >> 5) & 3);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -26,4 +26,4 @@ namespace ARMeilleure.Decoders
|
|||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,4 +11,4 @@ namespace ARMeilleure.Decoders
|
|||
Rm = opCode & 0xf;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -9,9 +9,9 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
public int Immediate { get; protected set; }
|
||||
|
||||
public bool Index { get; }
|
||||
public bool Add { get; }
|
||||
public bool WBack { get; }
|
||||
public bool Index { get; }
|
||||
public bool Add { get; }
|
||||
public bool WBack { get; }
|
||||
public bool Unprivileged { get; }
|
||||
|
||||
public bool IsLoad { get; }
|
||||
|
|
@ -24,16 +24,16 @@ namespace ARMeilleure.Decoders
|
|||
Rn = (opCode >> 16) & 0xf;
|
||||
|
||||
bool isLoad = (opCode & (1 << 20)) != 0;
|
||||
bool w = (opCode & (1 << 21)) != 0;
|
||||
bool u = (opCode & (1 << 23)) != 0;
|
||||
bool p = (opCode & (1 << 24)) != 0;
|
||||
bool w = (opCode & (1 << 21)) != 0;
|
||||
bool u = (opCode & (1 << 23)) != 0;
|
||||
bool p = (opCode & (1 << 24)) != 0;
|
||||
|
||||
Index = p;
|
||||
Add = u;
|
||||
WBack = !p || w;
|
||||
Index = p;
|
||||
Add = u;
|
||||
WBack = !p || w;
|
||||
Unprivileged = !p && w;
|
||||
|
||||
IsLoad = isLoad || inst.Name == InstName.Ldrd;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -9,4 +9,4 @@ namespace ARMeilleure.Decoders
|
|||
Immediate = opCode & 0xfff;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -12,4 +12,4 @@ namespace ARMeilleure.Decoders
|
|||
Immediate = imm4L | (imm4H << 4);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -7,8 +7,8 @@ namespace ARMeilleure.Decoders
|
|||
public int Rn { get; }
|
||||
|
||||
public int RegisterMask { get; }
|
||||
public int Offset { get; }
|
||||
public int PostOffset { get; }
|
||||
public int Offset { get; }
|
||||
public int PostOffset { get; }
|
||||
|
||||
public bool IsLoad { get; }
|
||||
|
||||
|
|
@ -19,9 +19,9 @@ namespace ARMeilleure.Decoders
|
|||
Rn = (opCode >> 16) & 0xf;
|
||||
|
||||
bool isLoad = (opCode & (1 << 20)) != 0;
|
||||
bool w = (opCode & (1 << 21)) != 0;
|
||||
bool u = (opCode & (1 << 23)) != 0;
|
||||
bool p = (opCode & (1 << 24)) != 0;
|
||||
bool w = (opCode & (1 << 21)) != 0;
|
||||
bool u = (opCode & (1 << 23)) != 0;
|
||||
bool p = (opCode & (1 << 24)) != 0;
|
||||
|
||||
RegisterMask = opCode & 0xffff;
|
||||
|
||||
|
|
@ -49,4 +49,4 @@ namespace ARMeilleure.Decoders
|
|||
IsLoad = isLoad;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,8 +2,8 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
class OpCode32Mrs : OpCode32
|
||||
{
|
||||
public bool R { get; }
|
||||
public int Rd { get; }
|
||||
public bool R { get; }
|
||||
public int Rd { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Mrs(inst, address, opCode);
|
||||
|
||||
|
|
|
|||
|
|
@ -4,11 +4,11 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
class OpCode32MsrReg : OpCode32
|
||||
{
|
||||
public bool R { get; }
|
||||
public int Mask { get; }
|
||||
public int Rd { get; }
|
||||
public bool R { get; }
|
||||
public int Mask { get; }
|
||||
public int Rd { get; }
|
||||
public bool Banked { get; }
|
||||
public int Rn { get; }
|
||||
public int Rn { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MsrReg(inst, address, opCode);
|
||||
|
||||
|
|
|
|||
|
|
@ -21,4 +21,4 @@ namespace ARMeilleure.Decoders
|
|||
ShiftType = (ShiftType)((opCode >> 5) & 2);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -15,4 +15,4 @@ namespace ARMeilleure.Decoders
|
|||
SatImm = (opCode >> 16) & 0xf;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -24,27 +24,21 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
protected int GetQuadwordIndex(int index)
|
||||
{
|
||||
switch (RegisterSize)
|
||||
return RegisterSize switch
|
||||
{
|
||||
case RegisterSize.Simd128:
|
||||
case RegisterSize.Simd64:
|
||||
return index >> 1;
|
||||
}
|
||||
|
||||
throw new InvalidOperationException();
|
||||
RegisterSize.Simd128 or RegisterSize.Simd64 => index >> 1,
|
||||
_ => throw new InvalidOperationException(),
|
||||
};
|
||||
}
|
||||
|
||||
protected int GetQuadwordSubindex(int index)
|
||||
{
|
||||
switch (RegisterSize)
|
||||
return RegisterSize switch
|
||||
{
|
||||
case RegisterSize.Simd128:
|
||||
return 0;
|
||||
case RegisterSize.Simd64:
|
||||
return index & 1;
|
||||
}
|
||||
|
||||
throw new InvalidOperationException();
|
||||
RegisterSize.Simd128 => 0,
|
||||
RegisterSize.Simd64 => index & 1,
|
||||
_ => throw new InvalidOperationException(),
|
||||
};
|
||||
}
|
||||
|
||||
protected OpCode32SimdBase(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode)
|
||||
|
|
|
|||
|
|
@ -15,8 +15,8 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
IsThumb = isThumb;
|
||||
|
||||
Op = ((opCode >> 16) & 0x1) != 0;
|
||||
T = ((opCode >> 7) & 0x1) != 0;
|
||||
Op = ((opCode >> 16) & 0x1) != 0;
|
||||
T = ((opCode >> 7) & 0x1) != 0;
|
||||
Size = ((opCode >> 8) & 0x1);
|
||||
|
||||
RegisterSize = Size == 1 ? RegisterSize.Int64 : RegisterSize.Int32;
|
||||
|
|
@ -41,4 +41,4 @@ namespace ARMeilleure.Decoders
|
|||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -14,9 +14,15 @@
|
|||
// The value must be a power of 2, otherwise it is the encoding of another instruction.
|
||||
switch (imm3h)
|
||||
{
|
||||
case 1: Size = 0; break;
|
||||
case 2: Size = 1; break;
|
||||
case 4: Size = 2; break;
|
||||
case 1:
|
||||
Size = 0;
|
||||
break;
|
||||
case 2:
|
||||
Size = 1;
|
||||
break;
|
||||
case 4:
|
||||
Size = 2;
|
||||
break;
|
||||
}
|
||||
|
||||
U = ((opCode >> (isThumb ? 28 : 24)) & 0x1) != 0;
|
||||
|
|
|
|||
|
|
@ -4,12 +4,12 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
class OpCode32SimdMemPair : OpCode32, IOpCode32Simd
|
||||
{
|
||||
private static int[] _regsMap =
|
||||
private static readonly int[] _regsMap =
|
||||
{
|
||||
1, 1, 4, 2,
|
||||
1, 1, 3, 1,
|
||||
1, 1, 2, 1,
|
||||
1, 1, 1, 1
|
||||
1, 1, 1, 1,
|
||||
};
|
||||
|
||||
public int Vd { get; }
|
||||
|
|
|
|||
|
|
@ -18,6 +18,6 @@
|
|||
Eq = 0,
|
||||
Vs,
|
||||
Ge,
|
||||
Gt
|
||||
Gt,
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -6,14 +6,14 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
public long Immediate { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAdr(inst, address, opCode);
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAdr(inst, address, opCode);
|
||||
|
||||
public OpCodeAdr(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Rd = opCode & 0x1f;
|
||||
|
||||
Immediate = DecoderHelper.DecodeImmS19_2(opCode);
|
||||
Immediate = DecoderHelper.DecodeImmS19_2(opCode);
|
||||
Immediate |= ((long)opCode >> 29) & 3;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,8 +11,8 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
public OpCodeAlu(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Rd = (opCode >> 0) & 0x1f;
|
||||
Rn = (opCode >> 5) & 0x1f;
|
||||
Rd = (opCode >> 0) & 0x1f;
|
||||
Rn = (opCode >> 5) & 0x1f;
|
||||
DataOp = (DataOp)((opCode >> 24) & 0x3);
|
||||
|
||||
RegisterSize = (opCode >> 31) != 0
|
||||
|
|
@ -20,4 +20,4 @@ namespace ARMeilleure.Decoders
|
|||
: RegisterSize.Int32;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,4 +11,4 @@ namespace ARMeilleure.Decoders
|
|||
Rm = (opCode >> 16) & 0x1f;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -33,8 +33,8 @@ namespace ARMeilleure.Decoders
|
|||
}
|
||||
else
|
||||
{
|
||||
throw new ArgumentException(nameof(opCode));
|
||||
throw new ArgumentException($"Invalid data operation: {DataOp}", nameof(opCode));
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ namespace ARMeilleure.Decoders
|
|||
class OpCodeAluRs : OpCodeAlu, IOpCodeAluRs
|
||||
{
|
||||
public int Shift { get; }
|
||||
public int Rm { get; }
|
||||
public int Rm { get; }
|
||||
|
||||
public ShiftType ShiftType { get; }
|
||||
|
||||
|
|
@ -22,8 +22,8 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
Shift = shift;
|
||||
|
||||
Rm = (opCode >> 16) & 0x1f;
|
||||
Rm = (opCode >> 16) & 0x1f;
|
||||
ShiftType = (ShiftType)((opCode >> 22) & 0x3);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ namespace ARMeilleure.Decoders
|
|||
class OpCodeAluRx : OpCodeAlu, IOpCodeAluRx
|
||||
{
|
||||
public int Shift { get; }
|
||||
public int Rm { get; }
|
||||
public int Rm { get; }
|
||||
|
||||
public IntType IntType { get; }
|
||||
|
||||
|
|
@ -11,9 +11,9 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
public OpCodeAluRx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Shift = (opCode >> 10) & 0x7;
|
||||
Shift = (opCode >> 10) & 0x7;
|
||||
IntType = (IntType)((opCode >> 13) & 0x7);
|
||||
Rm = (opCode >> 16) & 0x1f;
|
||||
Rm = (opCode >> 16) & 0x1f;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -8,4 +8,4 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
public OpCodeBImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -9,4 +9,4 @@ namespace ARMeilleure.Decoders
|
|||
Immediate = (long)address + DecoderHelper.DecodeImm26_2(opCode);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -17,4 +17,4 @@ namespace ARMeilleure.Decoders
|
|||
: RegisterSize.Int32;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -22,4 +22,4 @@ namespace ARMeilleure.Decoders
|
|||
Immediate = (long)address + DecoderHelper.DecodeImmS19_2(opCode);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
class OpCodeBImmTest : OpCodeBImm
|
||||
{
|
||||
public int Rt { get; }
|
||||
public int Rt { get; }
|
||||
public int Bit { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmTest(inst, address, opCode);
|
||||
|
|
@ -13,8 +13,8 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
Immediate = (long)address + DecoderHelper.DecodeImmS14_2(opCode);
|
||||
|
||||
Bit = (opCode >> 19) & 0x1f;
|
||||
Bit = (opCode >> 19) & 0x1f;
|
||||
Bit |= (opCode >> 26) & 0x20;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
public OpCodeBReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
int op4 = (opCode >> 0) & 0x1f;
|
||||
int op4 = (opCode >> 0) & 0x1f;
|
||||
int op2 = (opCode >> 16) & 0x1f;
|
||||
|
||||
if (op2 != 0b11111 || op4 != 0b00000)
|
||||
|
|
@ -21,4 +21,4 @@ namespace ARMeilleure.Decoders
|
|||
Rn = (opCode >> 5) & 0x1f;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,8 +4,8 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
public long WMask { get; }
|
||||
public long TMask { get; }
|
||||
public int Pos { get; }
|
||||
public int Shift { get; }
|
||||
public int Pos { get; }
|
||||
public int Shift { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBfm(inst, address, opCode);
|
||||
|
||||
|
|
@ -22,8 +22,8 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
WMask = bm.WMask;
|
||||
TMask = bm.TMask;
|
||||
Pos = bm.Pos;
|
||||
Pos = bm.Pos;
|
||||
Shift = bm.Shift;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
class OpCodeCcmp : OpCodeAlu, IOpCodeCond
|
||||
{
|
||||
public int Nzcv { get; }
|
||||
public int Nzcv { get; }
|
||||
protected int RmImm;
|
||||
|
||||
public Condition Cond { get; }
|
||||
|
|
@ -22,11 +22,11 @@ namespace ARMeilleure.Decoders
|
|||
return;
|
||||
}
|
||||
|
||||
Nzcv = (opCode >> 0) & 0xf;
|
||||
Cond = (Condition)((opCode >> 12) & 0xf);
|
||||
RmImm = (opCode >> 16) & 0x1f;
|
||||
Nzcv = (opCode >> 0) & 0xf;
|
||||
Cond = (Condition)((opCode >> 12) & 0xf);
|
||||
RmImm = (opCode >> 16) & 0x1f;
|
||||
|
||||
Rd = RegisterAlias.Zr;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -8,4 +8,4 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
public OpCodeCcmpImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -12,4 +12,4 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
public OpCodeCcmpReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { }
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -10,8 +10,8 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
public OpCodeCsel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Rm = (opCode >> 16) & 0x1f;
|
||||
Rm = (opCode >> 16) & 0x1f;
|
||||
Cond = (Condition)((opCode >> 12) & 0xf);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,4 +11,4 @@ namespace ARMeilleure.Decoders
|
|||
Id = (opCode >> 5) & 0xffff;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,18 +2,18 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
class OpCodeMem : OpCode
|
||||
{
|
||||
public int Rt { get; protected set; }
|
||||
public int Rn { get; protected set; }
|
||||
public int Size { get; protected set; }
|
||||
public int Rt { get; protected set; }
|
||||
public int Rn { get; protected set; }
|
||||
public int Size { get; protected set; }
|
||||
public bool Extend64 { get; protected set; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMem(inst, address, opCode);
|
||||
|
||||
public OpCodeMem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Rt = (opCode >> 0) & 0x1f;
|
||||
Rn = (opCode >> 5) & 0x1f;
|
||||
Rt = (opCode >> 0) & 0x1f;
|
||||
Rn = (opCode >> 5) & 0x1f;
|
||||
Size = (opCode >> 30) & 0x3;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3,14 +3,14 @@ namespace ARMeilleure.Decoders
|
|||
class OpCodeMemEx : OpCodeMem
|
||||
{
|
||||
public int Rt2 { get; }
|
||||
public int Rs { get; }
|
||||
public int Rs { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemEx(inst, address, opCode);
|
||||
|
||||
public OpCodeMemEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Rt2 = (opCode >> 10) & 0x1f;
|
||||
Rs = (opCode >> 16) & 0x1f;
|
||||
Rs = (opCode >> 16) & 0x1f;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,18 +2,18 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
class OpCodeMemImm : OpCodeMem
|
||||
{
|
||||
public long Immediate { get; protected set; }
|
||||
public bool WBack { get; protected set; }
|
||||
public bool PostIdx { get; protected set; }
|
||||
protected bool Unscaled { get; }
|
||||
public long Immediate { get; protected set; }
|
||||
public bool WBack { get; protected set; }
|
||||
public bool PostIdx { get; protected set; }
|
||||
protected bool Unscaled { get; }
|
||||
|
||||
private enum MemOp
|
||||
{
|
||||
Unscaled = 0,
|
||||
PostIndexed = 1,
|
||||
Unscaled = 0,
|
||||
PostIndexed = 1,
|
||||
Unprivileged = 2,
|
||||
PreIndexed = 3,
|
||||
Unsigned
|
||||
PreIndexed = 3,
|
||||
Unsigned,
|
||||
}
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemImm(inst, address, opCode);
|
||||
|
|
@ -21,13 +21,13 @@ namespace ARMeilleure.Decoders
|
|||
public OpCodeMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Extend64 = ((opCode >> 22) & 3) == 2;
|
||||
WBack = ((opCode >> 24) & 1) == 0;
|
||||
WBack = ((opCode >> 24) & 1) == 0;
|
||||
|
||||
// The type is not valid for the Unsigned Immediate 12-bits encoding,
|
||||
// because the bits 11:10 are used for the larger Immediate offset.
|
||||
MemOp type = WBack ? (MemOp)((opCode >> 10) & 3) : MemOp.Unsigned;
|
||||
|
||||
PostIdx = type == MemOp.PostIndexed;
|
||||
PostIdx = type == MemOp.PostIndexed;
|
||||
Unscaled = type == MemOp.Unscaled ||
|
||||
type == MemOp.Unprivileged;
|
||||
|
||||
|
|
@ -50,4 +50,4 @@ namespace ARMeilleure.Decoders
|
|||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,11 +2,11 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
class OpCodeMemLit : OpCode, IOpCodeLit
|
||||
{
|
||||
public int Rt { get; }
|
||||
public int Rt { get; }
|
||||
public long Immediate { get; }
|
||||
public int Size { get; }
|
||||
public bool Signed { get; }
|
||||
public bool Prefetch { get; }
|
||||
public int Size { get; }
|
||||
public bool Signed { get; }
|
||||
public bool Prefetch { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemLit(inst, address, opCode);
|
||||
|
||||
|
|
@ -18,11 +18,27 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
switch ((opCode >> 30) & 3)
|
||||
{
|
||||
case 0: Size = 2; Signed = false; Prefetch = false; break;
|
||||
case 1: Size = 3; Signed = false; Prefetch = false; break;
|
||||
case 2: Size = 2; Signed = true; Prefetch = false; break;
|
||||
case 3: Size = 0; Signed = false; Prefetch = true; break;
|
||||
case 0:
|
||||
Size = 2;
|
||||
Signed = false;
|
||||
Prefetch = false;
|
||||
break;
|
||||
case 1:
|
||||
Size = 3;
|
||||
Signed = false;
|
||||
Prefetch = false;
|
||||
break;
|
||||
case 2:
|
||||
Size = 2;
|
||||
Signed = true;
|
||||
Prefetch = false;
|
||||
break;
|
||||
case 3:
|
||||
Size = 0;
|
||||
Signed = false;
|
||||
Prefetch = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -8,11 +8,11 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
public OpCodeMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Rt2 = (opCode >> 10) & 0x1f;
|
||||
WBack = ((opCode >> 23) & 0x1) != 0;
|
||||
PostIdx = ((opCode >> 23) & 0x3) == 1;
|
||||
Rt2 = (opCode >> 10) & 0x1f;
|
||||
WBack = ((opCode >> 23) & 0x1) != 0;
|
||||
PostIdx = ((opCode >> 23) & 0x3) == 1;
|
||||
Extend64 = ((opCode >> 30) & 0x3) == 1;
|
||||
Size = ((opCode >> 31) & 0x1) | 2;
|
||||
Size = ((opCode >> 31) & 0x1) | 2;
|
||||
|
||||
DecodeImm(opCode);
|
||||
}
|
||||
|
|
@ -22,4 +22,4 @@ namespace ARMeilleure.Decoders
|
|||
Immediate = ((long)(opCode >> 15) << 57) >> (57 - Size);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@ namespace ARMeilleure.Decoders
|
|||
class OpCodeMemReg : OpCodeMem
|
||||
{
|
||||
public bool Shift { get; }
|
||||
public int Rm { get; }
|
||||
public int Rm { get; }
|
||||
|
||||
public IntType IntType { get; }
|
||||
|
||||
|
|
@ -11,10 +11,10 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
public OpCodeMemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Shift = ((opCode >> 12) & 0x1) != 0;
|
||||
IntType = (IntType)((opCode >> 13) & 0x7);
|
||||
Rm = (opCode >> 16) & 0x1f;
|
||||
Extend64 = ((opCode >> 22) & 0x3) == 2;
|
||||
Shift = ((opCode >> 12) & 0x1) != 0;
|
||||
IntType = (IntType)((opCode >> 13) & 0x7);
|
||||
Rm = (opCode >> 16) & 0x1f;
|
||||
Extend64 = ((opCode >> 22) & 0x3) == 2;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -22,9 +22,9 @@ namespace ARMeilleure.Decoders
|
|||
return;
|
||||
}
|
||||
|
||||
Rd = (opCode >> 0) & 0x1f;
|
||||
Immediate = (opCode >> 5) & 0xffff;
|
||||
Bit = (opCode >> 21) & 0x3;
|
||||
Rd = (opCode >> 0) & 0x1f;
|
||||
Immediate = (opCode >> 5) & 0xffff;
|
||||
Bit = (opCode >> 21) & 0x3;
|
||||
|
||||
Bit <<= 4;
|
||||
|
||||
|
|
@ -35,4 +35,4 @@ namespace ARMeilleure.Decoders
|
|||
: RegisterSize.Int32;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -13,4 +13,4 @@ namespace ARMeilleure.Decoders
|
|||
Rm = (opCode >> 16) & 0x1f;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,18 +2,18 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
class OpCodeSimd : OpCode, IOpCodeSimd
|
||||
{
|
||||
public int Rd { get; }
|
||||
public int Rn { get; }
|
||||
public int Opc { get; }
|
||||
public int Rd { get; }
|
||||
public int Rn { get; }
|
||||
public int Opc { get; }
|
||||
public int Size { get; protected set; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimd(inst, address, opCode);
|
||||
|
||||
public OpCodeSimd(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Rd = (opCode >> 0) & 0x1f;
|
||||
Rn = (opCode >> 5) & 0x1f;
|
||||
Opc = (opCode >> 15) & 0x3;
|
||||
Rd = (opCode >> 0) & 0x1f;
|
||||
Rn = (opCode >> 5) & 0x1f;
|
||||
Opc = (opCode >> 15) & 0x3;
|
||||
Size = (opCode >> 22) & 0x3;
|
||||
|
||||
RegisterSize = ((opCode >> 30) & 1) != 0
|
||||
|
|
@ -21,4 +21,4 @@ namespace ARMeilleure.Decoders
|
|||
: RegisterSize.Simd64;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ namespace ARMeilleure.Decoders
|
|||
public OpCodeSimdCvt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
int scale = (opCode >> 10) & 0x3f;
|
||||
int sf = (opCode >> 31) & 0x1;
|
||||
int sf = (opCode >> 31) & 0x1;
|
||||
|
||||
FBits = 64 - scale;
|
||||
|
||||
|
|
@ -18,4 +18,4 @@ namespace ARMeilleure.Decoders
|
|||
: RegisterSize.Int32;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -11,4 +11,4 @@ namespace ARMeilleure.Decoders
|
|||
Imm4 = (opCode >> 11) & 0xf;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
public OpCodeSimdFcond(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Nzcv = (opCode >> 0) & 0xf;
|
||||
Nzcv = (opCode >> 0) & 0xf;
|
||||
Cond = (Condition)((opCode >> 12) & 0xf);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
class OpCodeSimdFmov : OpCode, IOpCodeSimd
|
||||
{
|
||||
public int Rd { get; }
|
||||
public int Rd { get; }
|
||||
public long Immediate { get; }
|
||||
public int Size { get; }
|
||||
public int Size { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdFmov(inst, address, opCode);
|
||||
|
||||
|
|
@ -16,7 +16,7 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
long imm;
|
||||
|
||||
Rd = (opCode >> 0) & 0x1f;
|
||||
Rd = (opCode >> 0) & 0x1f;
|
||||
imm = (opCode >> 13) & 0xff;
|
||||
|
||||
if (type == 0)
|
||||
|
|
@ -29,4 +29,4 @@ namespace ARMeilleure.Decoders
|
|||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -52,17 +52,20 @@
|
|||
else if ((modeHigh & 0b110) == 0b100)
|
||||
{
|
||||
// 16-bits shifted Immediate.
|
||||
size = 1; imm <<= (modeHigh & 1) << 3;
|
||||
size = 1;
|
||||
imm <<= (modeHigh & 1) << 3;
|
||||
}
|
||||
else if ((modeHigh & 0b100) == 0b000)
|
||||
{
|
||||
// 32-bits shifted Immediate.
|
||||
size = 2; imm <<= modeHigh << 3;
|
||||
size = 2;
|
||||
imm <<= modeHigh << 3;
|
||||
}
|
||||
else if ((modeHigh & 0b111) == 0b110)
|
||||
{
|
||||
// 32-bits shifted Immediate (fill with ones).
|
||||
size = 2; imm = ShlOnes(imm, 8 << modeLow);
|
||||
size = 2;
|
||||
imm = ShlOnes(imm, 8 << modeLow);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
|
|||
|
|
@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
class OpCodeSimdImm : OpCode, IOpCodeSimd
|
||||
{
|
||||
public int Rd { get; }
|
||||
public int Rd { get; }
|
||||
public long Immediate { get; }
|
||||
public int Size { get; }
|
||||
public int Size { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdImm(inst, address, opCode);
|
||||
|
||||
|
|
@ -13,14 +13,14 @@ namespace ARMeilleure.Decoders
|
|||
Rd = opCode & 0x1f;
|
||||
|
||||
int cMode = (opCode >> 12) & 0xf;
|
||||
int op = (opCode >> 29) & 0x1;
|
||||
int op = (opCode >> 29) & 0x1;
|
||||
|
||||
int modeLow = cMode & 1;
|
||||
int modeLow = cMode & 1;
|
||||
int modeHigh = cMode >> 1;
|
||||
|
||||
long imm;
|
||||
|
||||
imm = ((uint)opCode >> 5) & 0x1f;
|
||||
imm = ((uint)opCode >> 5) & 0x1f;
|
||||
imm |= ((uint)opCode >> 11) & 0xe0;
|
||||
|
||||
if (modeHigh == 0b111)
|
||||
|
|
@ -67,17 +67,20 @@ namespace ARMeilleure.Decoders
|
|||
else if ((modeHigh & 0b110) == 0b100)
|
||||
{
|
||||
// 16-bits shifted Immediate.
|
||||
Size = 1; imm <<= (modeHigh & 1) << 3;
|
||||
Size = 1;
|
||||
imm <<= (modeHigh & 1) << 3;
|
||||
}
|
||||
else if ((modeHigh & 0b100) == 0b000)
|
||||
{
|
||||
// 32-bits shifted Immediate.
|
||||
Size = 2; imm <<= modeHigh << 3;
|
||||
Size = 2;
|
||||
imm <<= modeHigh << 3;
|
||||
}
|
||||
else if ((modeHigh & 0b111) == 0b110)
|
||||
{
|
||||
// 32-bits shifted Immediate (fill with ones).
|
||||
Size = 2; imm = ShlOnes(imm, 8 << modeLow);
|
||||
Size = 2;
|
||||
imm = ShlOnes(imm, 8 << modeLow);
|
||||
}
|
||||
else
|
||||
{
|
||||
|
|
@ -104,4 +107,4 @@ namespace ARMeilleure.Decoders
|
|||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -23,14 +23,22 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
switch (Size)
|
||||
{
|
||||
case 1: Size = 0; break;
|
||||
case 2: Size = 1; break;
|
||||
case 4: Size = 2; break;
|
||||
case 8: Size = 3; break;
|
||||
case 1:
|
||||
Size = 0;
|
||||
break;
|
||||
case 2:
|
||||
Size = 1;
|
||||
break;
|
||||
case 4:
|
||||
Size = 2;
|
||||
break;
|
||||
case 8:
|
||||
Size = 3;
|
||||
break;
|
||||
}
|
||||
|
||||
SrcIndex = imm4 >> Size;
|
||||
SrcIndex = imm4 >> Size;
|
||||
DstIndex = imm5 >> (Size + 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -25,4 +25,4 @@ namespace ARMeilleure.Decoders
|
|||
Extend64 = false;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,10 +2,10 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
class OpCodeSimdMemLit : OpCode, IOpCodeSimd, IOpCodeLit
|
||||
{
|
||||
public int Rt { get; }
|
||||
public int Rt { get; }
|
||||
public long Immediate { get; }
|
||||
public int Size { get; }
|
||||
public bool Signed => false;
|
||||
public int Size { get; }
|
||||
public bool Signed => false;
|
||||
public bool Prefetch => false;
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemLit(inst, address, opCode);
|
||||
|
|
@ -28,4 +28,4 @@ namespace ARMeilleure.Decoders
|
|||
Size = opc + 2;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,10 +2,10 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
class OpCodeSimdMemMs : OpCodeMemReg, IOpCodeSimd
|
||||
{
|
||||
public int Reps { get; }
|
||||
public int SElems { get; }
|
||||
public int Elems { get; }
|
||||
public bool WBack { get; }
|
||||
public int Reps { get; }
|
||||
public int SElems { get; }
|
||||
public int Elems { get; }
|
||||
public bool WBack { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemMs(inst, address, opCode);
|
||||
|
||||
|
|
@ -13,18 +13,41 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
switch ((opCode >> 12) & 0xf)
|
||||
{
|
||||
case 0b0000: Reps = 1; SElems = 4; break;
|
||||
case 0b0010: Reps = 4; SElems = 1; break;
|
||||
case 0b0100: Reps = 1; SElems = 3; break;
|
||||
case 0b0110: Reps = 3; SElems = 1; break;
|
||||
case 0b0111: Reps = 1; SElems = 1; break;
|
||||
case 0b1000: Reps = 1; SElems = 2; break;
|
||||
case 0b1010: Reps = 2; SElems = 1; break;
|
||||
case 0b0000:
|
||||
Reps = 1;
|
||||
SElems = 4;
|
||||
break;
|
||||
case 0b0010:
|
||||
Reps = 4;
|
||||
SElems = 1;
|
||||
break;
|
||||
case 0b0100:
|
||||
Reps = 1;
|
||||
SElems = 3;
|
||||
break;
|
||||
case 0b0110:
|
||||
Reps = 3;
|
||||
SElems = 1;
|
||||
break;
|
||||
case 0b0111:
|
||||
Reps = 1;
|
||||
SElems = 1;
|
||||
break;
|
||||
case 0b1000:
|
||||
Reps = 1;
|
||||
SElems = 2;
|
||||
break;
|
||||
case 0b1010:
|
||||
Reps = 2;
|
||||
SElems = 1;
|
||||
break;
|
||||
|
||||
default: Instruction = InstDescriptor.Undefined; return;
|
||||
default:
|
||||
Instruction = InstDescriptor.Undefined;
|
||||
return;
|
||||
}
|
||||
|
||||
Size = (opCode >> 10) & 3;
|
||||
Size = (opCode >> 10) & 3;
|
||||
WBack = ((opCode >> 23) & 1) != 0;
|
||||
|
||||
bool q = ((opCode >> 30) & 1) != 0;
|
||||
|
|
@ -45,4 +68,4 @@ namespace ARMeilleure.Decoders
|
|||
Elems = (GetBitsCount() >> 3) >> Size;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -13,4 +13,4 @@ namespace ARMeilleure.Decoders
|
|||
DecodeImm(opCode);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -18,4 +18,4 @@ namespace ARMeilleure.Decoders
|
|||
Extend64 = false;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,21 +2,21 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
class OpCodeSimdMemSs : OpCodeMemReg, IOpCodeSimd
|
||||
{
|
||||
public int SElems { get; }
|
||||
public int Index { get; }
|
||||
public int SElems { get; }
|
||||
public int Index { get; }
|
||||
public bool Replicate { get; }
|
||||
public bool WBack { get; }
|
||||
public bool WBack { get; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemSs(inst, address, opCode);
|
||||
|
||||
public OpCodeSimdMemSs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
int size = (opCode >> 10) & 3;
|
||||
int s = (opCode >> 12) & 1;
|
||||
int size = (opCode >> 10) & 3;
|
||||
int s = (opCode >> 12) & 1;
|
||||
int sElems = (opCode >> 12) & 2;
|
||||
int scale = (opCode >> 14) & 3;
|
||||
int l = (opCode >> 22) & 1;
|
||||
int q = (opCode >> 30) & 1;
|
||||
int scale = (opCode >> 14) & 3;
|
||||
int l = (opCode >> 22) & 1;
|
||||
int q = (opCode >> 30) & 1;
|
||||
|
||||
sElems |= (opCode >> 21) & 1;
|
||||
|
||||
|
|
@ -27,63 +27,63 @@ namespace ARMeilleure.Decoders
|
|||
switch (scale)
|
||||
{
|
||||
case 1:
|
||||
{
|
||||
if ((size & 1) != 0)
|
||||
{
|
||||
Instruction = InstDescriptor.Undefined;
|
||||
if ((size & 1) != 0)
|
||||
{
|
||||
Instruction = InstDescriptor.Undefined;
|
||||
|
||||
return;
|
||||
return;
|
||||
}
|
||||
|
||||
index >>= 1;
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
index >>= 1;
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
case 2:
|
||||
{
|
||||
if ((size & 2) != 0 ||
|
||||
((size & 1) != 0 && s != 0))
|
||||
{
|
||||
Instruction = InstDescriptor.Undefined;
|
||||
if ((size & 2) != 0 ||
|
||||
((size & 1) != 0 && s != 0))
|
||||
{
|
||||
Instruction = InstDescriptor.Undefined;
|
||||
|
||||
return;
|
||||
return;
|
||||
}
|
||||
|
||||
if ((size & 1) != 0)
|
||||
{
|
||||
index >>= 3;
|
||||
|
||||
scale = 3;
|
||||
}
|
||||
else
|
||||
{
|
||||
index >>= 2;
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
if ((size & 1) != 0)
|
||||
{
|
||||
index >>= 3;
|
||||
|
||||
scale = 3;
|
||||
}
|
||||
else
|
||||
{
|
||||
index >>= 2;
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
case 3:
|
||||
{
|
||||
if (l == 0 || s != 0)
|
||||
{
|
||||
Instruction = InstDescriptor.Undefined;
|
||||
if (l == 0 || s != 0)
|
||||
{
|
||||
Instruction = InstDescriptor.Undefined;
|
||||
|
||||
return;
|
||||
return;
|
||||
}
|
||||
|
||||
scale = size;
|
||||
|
||||
Replicate = true;
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
scale = size;
|
||||
|
||||
Replicate = true;
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
Index = index;
|
||||
Index = index;
|
||||
SElems = sElems;
|
||||
Size = scale;
|
||||
Size = scale;
|
||||
|
||||
Extend64 = false;
|
||||
|
||||
|
|
@ -94,4 +94,4 @@ namespace ARMeilleure.Decoders
|
|||
: RegisterSize.Simd64;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -3,16 +3,16 @@ namespace ARMeilleure.Decoders
|
|||
class OpCodeSimdReg : OpCodeSimd
|
||||
{
|
||||
public bool Bit3 { get; }
|
||||
public int Ra { get; }
|
||||
public int Rm { get; protected set; }
|
||||
public int Ra { get; }
|
||||
public int Rm { get; protected set; }
|
||||
|
||||
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdReg(inst, address, opCode);
|
||||
|
||||
public OpCodeSimdReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Bit3 = ((opCode >> 3) & 0x1) != 0;
|
||||
Ra = (opCode >> 10) & 0x1f;
|
||||
Rm = (opCode >> 16) & 0x1f;
|
||||
Bit3 = ((opCode >> 3) & 0x1) != 0;
|
||||
Ra = (opCode >> 10) & 0x1f;
|
||||
Rm = (opCode >> 16) & 0x1f;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
case 1:
|
||||
Index = (opCode >> 20) & 3 |
|
||||
(opCode >> 9) & 4;
|
||||
(opCode >> 9) & 4;
|
||||
|
||||
Rm &= 0xf;
|
||||
|
||||
|
|
@ -24,8 +24,10 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
break;
|
||||
|
||||
default: Instruction = InstDescriptor.Undefined; break;
|
||||
default:
|
||||
Instruction = InstDescriptor.Undefined;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -26,7 +26,9 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
break;
|
||||
|
||||
default: Instruction = InstDescriptor.Undefined; break;
|
||||
default:
|
||||
Instruction = InstDescriptor.Undefined;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -9,4 +9,4 @@ namespace ARMeilleure.Decoders
|
|||
Size = ((opCode >> 13) & 3) + 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@ namespace ARMeilleure.Decoders
|
|||
{
|
||||
class OpCodeSystem : OpCode
|
||||
{
|
||||
public int Rt { get; }
|
||||
public int Rt { get; }
|
||||
public int Op2 { get; }
|
||||
public int CRm { get; }
|
||||
public int CRn { get; }
|
||||
|
|
@ -13,12 +13,12 @@ namespace ARMeilleure.Decoders
|
|||
|
||||
public OpCodeSystem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Rt = (opCode >> 0) & 0x1f;
|
||||
Op2 = (opCode >> 5) & 0x7;
|
||||
CRm = (opCode >> 8) & 0xf;
|
||||
CRn = (opCode >> 12) & 0xf;
|
||||
Op1 = (opCode >> 16) & 0x7;
|
||||
Rt = (opCode >> 0) & 0x1f;
|
||||
Op2 = (opCode >> 5) & 0x7;
|
||||
CRm = (opCode >> 8) & 0xf;
|
||||
CRn = (opCode >> 12) & 0xf;
|
||||
Op1 = (opCode >> 16) & 0x7;
|
||||
Op0 = ((opCode >> 19) & 0x1) | 2;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -12,4 +12,4 @@ namespace ARMeilleure.Decoders
|
|||
OpCodeSizeInBytes = 2;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
namespace ARMeilleure.Decoders
|
||||
{
|
||||
class OpCodeT16AddSubImm3: OpCodeT16, IOpCode32AluImm
|
||||
class OpCodeT16AddSubImm3 : OpCodeT16, IOpCode32AluImm
|
||||
{
|
||||
public int Rd { get; }
|
||||
public int Rn { get; }
|
||||
|
|
@ -15,8 +15,8 @@
|
|||
|
||||
public OpCodeT16AddSubImm3(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
Rd = (opCode >> 0) & 0x7;
|
||||
Rn = (opCode >> 3) & 0x7;
|
||||
Rd = (opCode >> 0) & 0x7;
|
||||
Rn = (opCode >> 3) & 0x7;
|
||||
Immediate = (opCode >> 6) & 0x7;
|
||||
IsRotated = false;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
|
||||
public OpCodeT16BImm11(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
|
||||
{
|
||||
int imm = (opCode << 21) >> 20;
|
||||
int imm = (opCode << 21) >> 20;
|
||||
Immediate = GetPc() + imm;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Add table
Add a link
Reference in a new issue